ZHCSA87F August 2012 – June 2019 DLP7000
Table 3 lists the available controls and status pin names and their corresponding signal type, along with a brief functional description.
|DDC_DOUT_[A,B,C,D](15:0)||LVDS DDR output to DMD data bus A,B,C,D (15:0)||O|
|DDC_DCLKOUT_[A,B,C,D]||LVDS output to DMD data clock A,B,C,D||O|
|DDC_SCTRL_[A,B,C,D]||LVDS DDR output to DMD data control A,B,C,D||O|