ZHCSN33C November   2017  – December 2024 DLP550JE

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements
    8. 5.8  Window Characteristics
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Feature Description
      1. 6.2.1 Power Interface
      2. 6.2.2 Timing
    3. 6.3 Optical Interface and System Image Quality Considerations
      1. 6.3.1 Numerical Aperture and Stray Light Control
      2. 6.3.2 Pupil Match
      3. 6.3.3 Illumination Overfill
    4. 6.4 Micromirror Array Temperature Calculation
      1. 6.4.1 Micromirror Array Temperature Calculation
    5. 6.5 Micromirror Power Density Calculation
    6. 6.6 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 6.6.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.6.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.6.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.6.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power-Up and Power-Down Procedures
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 第三方产品免责声明
      2. 9.1.2 Device Nomenclature
      3. 9.1.3 Device Markings
    2. 9.2 支持资源
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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5.7 Timing Requirements

Over operating free-air temperature range (unless otherwise noted).
MINNOMMAXUNIT
LVDS(1)
tcClock Cycle for DLCK_A3.03ns
tcClock Cycle for DCLKC_B3.03ns
twPulse Duration DCLK_A1.361.52ns
twPulse Duration for DCLK_B1.361.52ns
tSUSetup Time, D_A[0:15] before DCLK_A0.35ns
tSUSetup Time, D_B[0:15] before DCLK_B0.35ns
tSUSetup Time, SCTRL_A before DCLK_A0.35ns
tSUSetup Time, SCTRL_B before DCLK_B0.35ns
tHHold Time, D_A[0:15] after DCLK_A0.35ns
tHHold Time, D_B[0:15] after DCLK_B0.35ns
tHHold Time, SCTRL_A after DCLK_A0.35ns
tHHold Time, SCTRL_B after DCLK_B0.35ns
tskewChannel B relative to Channel A(2)(3)–1.511.51ns
(1) See Figure 5-5 for timing requirements for LVDS.
(2) Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15:0) and D_AP(15:0).
(3) Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15:0) and D_BP(15:0).
DLP550JE SCP Timing Parameters Figure 5-2 SCP Timing Parameters
DLP550JE Rise Time and Fall Time
Not to scale
Refer to Section 5.7.
Refer to Section 4 for list of LVDS pins and SCP pins.
Figure 5-3 Rise Time and Fall Time
DLP550JE Test Load Circuit for Output Propagation MeasurementFigure 5-4 Test Load Circuit for Output Propagation Measurement

For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. System design should use IBIS or other simulation tools to correlate the timing reference load to a system environment. See Figure 5-4.

DLP550JE Timing RequirementsFigure 5-5 Timing Requirements
DLP550JE Serial Communications Bus Waveform RequirementsFigure 5-6 Serial Communications Bus Waveform Requirements
DLP550JE LVDS Voltage Definitions (References)
Refer to LVDS Interface section of Section 5.4.
Refer to Section 4 for list of LVDS pins.
Figure 5-7 LVDS Voltage Definitions (References)
DLP550JE LVDS Voltage Parameter
Not to scale
Refer to LVDS Interface section of the Section 5.4.
Figure 5-8 LVDS Voltage Parameter
DLP550JE LVDS Equivalent Input Circuit
Refer to LVDS Interface section of the Section 5.4.
Refer to Section 4 for list of LVDS pins.
Figure 5-9 LVDS Equivalent Input Circuit