ZHCSJA3B January 2019 – May 2022 DLP4500NIR
Electrically, the DLP4500NIR device consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid of 912 memory cell columns by 1140 memory cell rows. The CMOS memory array is addressed on a column-by-column basis, over a 24-bit DDR bus. Addressing is handled through a serial control bus. The specific CMOS memory access protocol is handled by the DLPC350 digital controller.
Optically, the DLP4500NIR device consists of 1039680 highly reflective, digitally switchable, micrometer-sized mirrors (micromirrors) organized in a two-dimensional array. The micromirror array consists of 912 micromirror columns by 1140 micromirror rows in diamond pixel configuration (Figure 8-1). Due to the diamond pixel configuration, the columns of each odd row are offset by half a pixel from the columns of the even row.