ZHCSJA3B January   2019  – May 2022 DLP4500NIR

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 Revision History
  5. 5 Chipset Component Usage Specification
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  Timing Requirements
    8. 7.8  System Mounting Interface Loads
    9. 7.9  Micromirror Array Physical Characteristics
    10. 7.10 Micromirror Array Optical Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes
    5. 8.5 Micromirror Array Temperature Calculation
      1. 8.5.1 Package Thermal Resistance
      2. 8.5.2 Case Temperature
        1. 8.5.2.1 Temperature Calculation
    6. 8.6 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 8.6.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.6.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.6.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.6.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 DLPC350 System Interfaces
          1. 9.2.2.1.1 Control Interface
          2. 9.2.2.1.2 Input Data Interface
        2. 9.2.2.2 DLPC350 System Output Interfaces
          1. 9.2.2.2.1 Illumination Interface
          2. 9.2.2.2.2 Trigger Interface (Sync Outputs)
        3. 9.2.2.3 DLPC350 System Support Interfaces
          1. 9.2.2.3.1 Reference Clock
          2. 9.2.2.3.2 PLL
          3. 9.2.2.3.3 Program Memory Flash Interface
        4. 9.2.2.4 DMD Interfaces
          1. 9.2.2.4.1 DLPC350 to DMD Digital Data
          2. 9.2.2.4.2 DLPC350 to DMD Control Interface
          3. 9.2.2.4.3 DLPC350 to DMD Micromirror Reset Control Interface
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing Requirements
    2. 10.2 DMD Power Supply Power-Up Procedure
    3. 10.3 DMD Power Supply Power-Down Procedure
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DMD Interface Design Considerations
      2. 11.1.2 DMD Termination Requirements
      3. 11.1.3 Decoupling Capacitors
      4. 11.1.4 Power Plane Recommendations
      5. 11.1.5 Signal Layer Recommendations
      6. 11.1.6 General Handling Guidelines for CMOS-Type Pins
      7. 11.1.7 PCB Manufacturing
        1. 11.1.7.1 General Guidelines
        2. 11.1.7.2 Trace Widths and Minimum Spacings
        3. 11.1.7.3 Routing Constraints
        4. 11.1.7.4 Fiducials
        5. 11.1.7.5 Flex Considerations
        6. 11.1.7.6 DLPC350 Thermal Considerations
    2. 11.2 Layout Example
      1. 11.2.1 Printed Circuit Board Layer Stackup Geometry
      2. 11.2.2 Recommended DLPC350 MOSC Crystal Oscillator Configuration
      3. 11.2.3 Recommended DLPC350 PLL Layout Configuration
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 第三方产品免责声明
      2. 12.1.2 Device Nomenclature
      3. 12.1.3 Device Markings
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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9.2.2.1.1 Control Interface

The DLP4500NIR chipset accepts control interface commands via the I2C or USB input buses. The control interface allows another master processor to send commands to the DLP4500NIR chipset to query system status or perform realtime operations such as programming LED driver current settings.

The DLPC350 controller offers two different sets of slave addresses. The I2C_ADDR_SEL pin provides the ability to select an alternate set of 7-bit I2C slave addresses only during power-up. If the I2C_ADDR_SEL pin is set low (logic '0'), then the DLPC350 slave addresses are 0x34 and 0x35. If the I2C-ADDR_SEL pin is set high (logic '1'), then the DLPC350 slave address is 0x3A and 0x3B. The I2C_ADDR_SEL pin also changes the serial number for the USB device so that two DLPC350s can be connected to one computer through USB. Once the system initialization is complete, this pin is available as a GPIO. See the DLPC350 Programmer's Guide (listed in Section 12.2.1) for detailed information about these operations.

Table 9-1 lists a description for active signals used by the DLPC350 to support the I2C interface.

Table 9-1 Active Signals – I2C Interface
Signal NameDescription
I2C1_SCLI2C clock. Bidirectional open-drain signal. I2C slave clock input from the external processor.
I2C1_SDAI2C data. Bidirectional open-drain signal. I2C slave to accept command or transfer data to and from the external processor.
I2C0_SCLI2C bus 0, clock; I2C master for on-board peripherals
I2C0_SDAI2C bus 0, data; I2C master for on-board peripherals