ZHCSJN3B March   2019  – May 2022 DLP2000

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  System Mounting Interface Loads
    9. 6.9  Physical Characteristics of the Micromirror Array
    10. 6.10 Micromirror Array Optical Characteristics
    11. 6.11 Window Characteristics
    12. 6.12 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Control Serial Interface
      3. 7.3.3 High Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Window Characteristics and Optics
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 第三方产品免责声明
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Related Links
    4. 11.4 接收文档更新通知
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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9.2 Power Supply Power-Down Procedure

  • The power-down sequence is the reverse order of the previous power-up sequence. VCC must be supplied until after VBIAS, VRESET and VOFFSET are discharged to within 4 V of ground.
  • During Power-Down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement that the delta between VBIAS and VOFFSET must be within ±8.75 V (Note 1).
  • During power-down, the DMD’s LVCMOS input pins must be less than VCC + 0.3 V.
  • During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS.
  • Slew rates for power-down are flexible, as long as the transient voltage levels follow the requirements listed previously.
GUID-87FE8535-48CF-4B0C-8ECF-671FDB3F5F83-low.gifFigure 9-1 DMD Power Supply Sequencing Requirements

Note 1: Refer to specifications listed in Section 6.4. Waveforms are not to scale. Details are omitted for clarity.

Note 2: DMD_PWR_EN is not a package pin on the DMD. It is a signal from the DLP Display Controller (DLPC2607) that enables the VRESET, VBIAS, and VOFFSET regulators on the system board.

Note 3: After the DMD micromirror park sequence is complete, the DLP display controller (DLPC2607) software initiates a hardware power-down that disables VBIAS, VRESET and VOFFSET.

Note 4: During the micromirror parking process, VCC, VBIAS, VOFFSET, and VRESET power supplies are all required to be within the specification limits in Section 6.4. Once the micromirrors are parked, VBIAS, VOFFSET, and VRESET power supplies can be turned off.

Note 5: To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in Section 6.4. It is critical to meet this requirement and that VBIAS not reach full power level until after VOFFSET is at almost full power level. OEMs may find that the most reliable way to ensure this is to delay powering VBIAS until after VOFFSET is fully powered on during power-up (and to remove VBIAS prior to VOFFSET during power down). In this case, VOFFSET is run at its maximum allowable voltage level (8.75 V).

Note 6: Refer to specifications listed in Table 9-1.

Table 9-1 DMD Power-Down Sequence Requirements
PARAMETERDESCRIPTIONMINMAXUNIT
VBIASSupply voltage level during power-down sequence4.0V
VOFFSETSupply voltage level during power-down sequence4.0V
VRESETSupply voltage level during power-down sequence–4.00.5V