ZHCSJN3B March   2019  – May 2022 DLP2000

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  System Mounting Interface Loads
    9. 6.9  Physical Characteristics of the Micromirror Array
    10. 6.10 Micromirror Array Optical Characteristics
    11. 6.11 Window Characteristics
    12. 6.12 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Control Serial Interface
      3. 7.3.3 High Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Window Characteristics and Optics
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 第三方产品免责声明
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Related Links
    4. 11.4 接收文档更新通知
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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订购信息

5 Pin Configuration and Functions

GUID-9EBECA09-36A3-4B39-BA08-030877E1B072-low.gifFigure 5-1 FQC Package42-Pin LGABottom View
Table 5-1 Pin Functions
PIN TYPE SIGNAL DATA RATE DESCRIPTION PACKAGE NET LENGTH (mm)
NAME NO.
DATA INPUTS
DATA(0) J13 Input LVCMOS DDR Input data bus 8.83
DATA(1) J2 Input LVCMOS DDR Input data bus 7.53
DATA(2) J4 Input LVCMOS DDR Input data bus 6.96
DATA(3) J6 Input LVCMOS DDR Input data bus 7.05
DATA(4) J7 Input LVCMOS DDR Input data bus 7.56
DATA(5) J8 Input LVCMOS DDR Input data bus 7.07
DATA(6) J12 Input LVCMOS DDR Input data bus 7.61
DATA(7) J10 Input LVCMOS DDR Input data bus 7.68
DATA(8) K4 Input LVCMOS DDR Input data bus 7.31
DATA(9) K2 Input LVCMOS DDR Input data bus 6.76
DATA(10) K7 Input LVCMOS DDR Input data bus 8.18
DATA(11) K6 Input LVCMOS DDR Input data bus 7.81
DCLK K9 Input LVCMOS Input data clock 7.78
CONTROL INPUTS
LOADB K10 Input LVCMOS DDR Parallel latch load enable 7.64
SCTRL K12 Input LVCMOS DDR Serial control (sync) 8.62
DRC_BUS K14 Input LVCMOS Reset control serial bus. synchronous to rising edge of DCLK. Bond pad does not connect to internal pull down. 7.28
DRC_OEZ K18 Input LVCMOS Active low. Output enable signal for internal reset driver circuitry. Bond pads do not connect to internal pulldown. 4.69
DRC_STROBE J15 Input LVCMOS Rising edge on DRC_STROBE latches in the control signals. Synchronous to rising edge of DCLK. Bond pad does not connect to internal pulldown. 7.61
SAC_BUS K16 Input LVCMOS Stepped address control serial bus. Synchronous to rising edge of DCLK. Bond pad does not connect to internal pulldown. 8.17
SCAN_TEST K20 Input LVCMOS MUX’ed output for scanned chip ID 1.18
POWER
VBIAS J16 Power Power supply for positive bias level of mirror reset signal
VOFFSET K15 Power Power supply for high voltage CMOS logic. Power supply for stepped high voltage at mirror address electrodes. Power supply for offset level of mirror reset signal
VRESET J20 Power Power supply for negative reset level of mirror reset signal
VCC J1 Power Power supply for low voltage CMOS logic. Power supply for normal high voltage at mirror address electrodes. Power supply for offset level of mirror reset signal during power down
VCC J11 Power
VCC J21 Power
VCC K1 Power
VCC K11 Power
VCC K21 Power
VSS J3 Power Common return. Ground for all power
VSS J5 Power
VSS J9 Power
VSS J14 Power
VSS J17 Power
VSS J18 Power
VSS J19 Power
VSS K3 Power
VSS K5 Power
VSS K8 Power
VSS K13 Power
VSS K17 Power
VSS K19 Power
Pin Functions—Test Pads
Electrical Test Pad DLP® System Board
A1 Do not connect.
A3 Do not connect.
A5 Do not connect.
A7 Do not connect.
A9 Do not connect.
A11 Do not connect.
A13 Do not connect.
A15 Do not connect.
A17 Do not connect.
A19 Do not connect.
A21 Do not connect.
A23 Do not connect.
A25 Do not connect.
A27 Do not connect.
A29 Do not connect.
A31 Do not connect.
A33 Do not connect.
A35 Do not connect.
A37 Do not connect.
A39 Do not connect.
A41 Do not connect.
B2 Do not connect.
B4 Do not connect.
B6 Do not connect.
B38 Do not connect.
C3 Do not connect.
D4 Do not connect.
E4 Do not connect.
F3 Do not connect.
G2 Do not connect.
G4 Do not connect.
G6 Do not connect.
G38 Do not connect.
H1 Do not connect.
H3 Do not connect.
H5 Do not connect.
H7 Do not connect.
H9 Do not connect.
H11 Do not connect.
H13 Do not connect.
H15 Do not connect.
H17 Do not connect.
H19 Do not connect.
H21 Do not connect.
H23 Do not connect.
H25 Do not connect.
H27 Do not connect.
H29 Do not connect.
H31 Do not connect.
H33 Do not connect.
H35 Do not connect.
H37 Do not connect.
H39 Do not connect.
H41 Do not connect.