ZHCSP44D October   2021  – October 2024 DLP160CP

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements
    8. 5.8  Switching Characteristics
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Low-Speed Interface
      3. 6.3.3 High-Speed Interface
      4. 6.3.4 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application—nHD Mode
      2. 7.2.2 Typical Application—HD Mode
      3. 7.2.3 Design Requirements
      4. 7.2.4 Detailed Design Procedure
      5. 7.2.5 Application Curve
  9. 8 Power Supply Recommendations
    1. 8.1 Power Supply Power-Up Procedure
    2. 8.2 Power Supply Power-Down Procedure
    3. 8.3 Power Supply Sequencing Requirements
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方产品免责声明
      2. 10.1.2 Device Nomenclature
      3. 10.1.3 Device Markings
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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5.7 Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
MINNOMMAXUNIT
LPSDR
trRise slew rate(1)(30% to 80%) × VDD, Figure 5-313V/ns
tƒFall slew rate(1)(70% to 20%) × VDD, Figure 5-313V/ns
trRise slew rate(2)(20% to 80%) × VDD, Figure 5-30.25V/ns
tƒFall slew rate(2)(80% to 20%) × VDD, Figure 5-30.25V/ns
tcCycle time LS_CLKFigure 5-27.78.3ns
tW(H)Pulse duration LS_CLK high50% to 50% reference points, Figure 5-23.1ns
tW(L)Pulse duration LS_CLK low50% to 50% reference points, Figure 5-23.1ns
tsuSetup timeLS_WDATA valid before LS_CLK ↑, Figure 5-21.5ns
thHold timeLS_WDATA valid after LS_CLK ↑, Figure 5-21.5ns
tWINDOWWindow time(1) (3)Setup time + hold time, Figure 5-23ns
tDERATINGWindow time derating(1) (3)For each 0.25V/ns reduction in slew rate below 1V/ns, Figure 5-50.35ns
SubLVDS
trRise slew rate20% to 80% reference points, Figure 5-40.71V/ns
tƒFall slew rate80% to 20% reference points, Figure 5-40.71V/ns
tcCycle time DCLKFigure 5-61.791.85ns
tW(H)Pulse duration DCLK high50% to 50% reference points, Figure 5-60.79ns
tW(L)Pulse duration DCLK low50% to 50% reference points, Figure 5-60.79ns
tsuSetup timeD(0:7) valid before
DCLK ↑ or DCLK ↓, Figure 5-6

Setup and Hold times are defined by tWINDOW

thHold timeD(0:7) valid after
DCLK ↑ or DCLK ↓, Figure 5-6

Setup and Hold times are defined by tWINDOW

tWINDOWWindow timeSetup time + hold time, Figure 5-6, Figure 5-70.3ns
tLVDS-ENABLE+REFGENPower-up receiver(4)2000ns
(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 5-3.
(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 5-3.
(3) Window time derating example: 0.5V/ns slew rate increases the window time by 0.7ns, from 3ns to 3.7ns.
(4) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
DLP160CP LPSDR Switching Parameters
Low-speed interface is LPSDR and adheres to the Section 5.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.
Figure 5-2 LPSDR Switching Parameters
DLP160CP LPSDR Input Rise and Fall Slew RateFigure 5-3 LPSDR Input Rise and Fall Slew Rate
DLP160CP SubLVDS Input Rise and Fall Slew RateFigure 5-4 SubLVDS Input Rise and Fall Slew Rate
DLP160CP Window Time Derating ConceptFigure 5-5 Window Time Derating Concept
DLP160CP SubLVDS Switching ParametersFigure 5-6 SubLVDS Switching Parameters
DLP160CP High-Speed Training Scan Window
Note: Refer to Section 6.3.3 for details.
Figure 5-7 High-Speed Training Scan Window
DLP160CP SubLVDS Voltage ParametersFigure 5-8 SubLVDS Voltage Parameters
DLP160CP SubLVDS Waveform ParametersFigure 5-9 SubLVDS Waveform Parameters
DLP160CP SubLVDS Equivalent Input CircuitFigure 5-10 SubLVDS Equivalent Input Circuit
DLP160CP LPSDR Input HysteresisFigure 5-11 LPSDR Input Hysteresis
DLP160CP LPSDR Read OutFigure 5-12 LPSDR Read Out
DLP160CP Test Load Circuit for Output Propagation Measurement
See Section 6.3.4 for more information.
Figure 5-13 Test Load Circuit for Output Propagation Measurement