ZHCSKJ2A November   2019  – April 2020 DAC60502 , DAC70502 , DAC80502


  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      功能方框图
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements : SPI Mode
    7. 7.7  Timing Requirements : I2C Standard Mode
    8. 7.8  Timing Requirements : I2C Fast Mode
    9. 7.9  Timing Requirements : I2C Fast-Mode Plus
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. DAC Transfer Function
        2. DAC Register Structure
        3. Output Amplifier
      2. 8.3.2 Internal Reference
        1. Solder Heat Reflow
      3. 8.3.3 Power-On Reset (POR)
      4. 8.3.4 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. SPI Mode
          1. SYNC Interrupt
        2. I2C Mode
          1. F/S Mode Protocol
          2. DACx0502 I2C Update Sequence
            1. DACx0502 Address Byte
            2. DACx0502 Command Byte
            3. DACx0502 Data Byte (MSDB and LSDB)
          3. DACx0502 I2C Read Sequence
    6. 8.6 Register Maps
      1. 8.6.1 Registers
        1. NOOP Register (offset = 0h) [reset = 0000h]
          1. Table 9. NOOP Register Field Descriptions
        2. DEVID Register (offset = 1h) [reset = 0214h for DAC80502, 1214h for DAC70502, 2214h for DAC60502]
          1. Table 10. DEVID Register Field Descriptions
        3. SYNC Register (offset = 2h) [reset = 0300h]
          1. Table 11. SYNC Register Field Descriptions
        4. CONFIG Register (offset = 3h) [reset = 0000h]
          1. Table 12. CONFIG Register Field Descriptions
        5. GAIN Register (offset = 4h) [reset = 0003h]
          1. Table 13. GAIN Register Field Descriptions
        6. TRIGGER Register (offset = 5h) [reset = 0000h]
          1. Table 14. TRIGGER Register Field Descriptions
        7. BRDCAST Register (offset = 6h) [reset = 0000h for RSTSEL = 0, or reset = 8000h for RSTSEL = 1]
          1. Table 15. BRDCAST Register Field Descriptions
        8. STATUS Register (offset = 7h) [reset = 0000h]
          1. Table 16. STATUS Register Field Descriptions
        9. DAC-n Register (offset = 8h–9h) [reset = 0000h for RSTSEL = 0, or reset = 8000h for RSTSEL = 1]
          1. Table 17. DAC-A Data Register Field Descriptions (8h)
          2. Table 18. DAC-B Data Register Field Descriptions (9h)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 SPI Connection to a Processor
      2. 9.3.2 I2C Interface Connection to a Processor
    4. 9.4 What To Do and What Not To Do
      1. 9.4.1 What To Do
      2. 9.4.2 What Not To Do
    5. 9.5 Initialization Setup
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 相关链接
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息


机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

I2C Mode

The DACx0502 digital interface is programmed to work in I2C mode when the logic level of the SPI2C pin is 1 at power up. In I2C mode, the DACx0502 have a 2-wire serial interface: SCL, SDA, and one address pin, A0. The I2C bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both the SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through open-drain I/O pins SDA and SCL.

The I2C specification states that the device that controls communication is called a master, and the devices that are controlled by the master are called slaves. The master device generates the SCL signal. The master device also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus to indicate the start or stop of a data transfer. Device addressing is completed by the master. The master device on an I2C bus is typically a microcontroller or DSP. The DACx0502 operate as a slave device on the I2C bus. A slave device acknowledges master commands, and upon master control, receives or transmits data.

Typically, the DACx0502 operate as a slave receiver. A master device writes to the DACx0502, a slave receiver. However, if a master device requires the DACx0502 internal register data, the DACx0502 operate as a slave transmitter. In this case, the master device reads from the DACx0502 According to I2C terminology, read and write refer to the master device.

The DACx0502 are slave devices that support the following data transfer modes:

  1. Standard mode (100 kbps)
  2. Fast mode (400 kbps)
  3. Fast-mode plus (1.0 Mbps)

The data transfer protocol for standard and fast modes is exactly the same; therefore, these modes are referred to as F/S-mode in this document. The fast-mode plus protocol is supported in terms of data transfer speed, but not output current. The low-level output current would be 3 mA, similar to the case of standard and fast modes. The DACx0502 support 7-bit addressing. The 10-bit addressing mode is not supported. These devices support the general call reset function. Sending the following sequence initiates a software reset within the device: start/repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the falling edge of the ACK bit, following the second byte.

Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a ninth clock cycle generates and detects an acknowledge signal. Acknowledge is when the SDA line is pulled low during the high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the high period of the ninth clock cycle as shown in Figure 59.

DAC80502 DAC70502 DAC60502 SBAS793_DACx0502_ACK.gifFigure 59. Acknowledge and Not Acknowledge on the I2C Bus