ZHCSRA2 December   2022 DAC53204W , DAC63204W

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 规格
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Current Output
    7. 6.7  Electrical Characteristics: Comparator Mode
    8. 6.8  Electrical Characteristics: General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 6.15 Timing Requirements: GPIO
    16. 6.16 Timing Diagrams
    17. 6.17 Typical Characteristics: Voltage Output
    18. 6.18 Typical Characteristics: Current Output
    19. 6.19 Typical Characteristics: Comparator
    20. 6.20 Typical Characteristics: General
  7. 7 详细说明
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 特性说明
      1. 7.3.1 智能数模转换器 (DAC) 架构
      2. 7.3.2 数字输入/输出
      3. 7.3.3 Nonvolatile Memory (NVM)
    4. 7.4 器件功能模式
      1. 7.4.1 电压输出模式
        1. 7.4.1.1 电压基准和 DAC 传递函数
          1. 7.4.1.1.1 Internal Reference
          2. 7.4.1.1.2 External Reference
          3. 7.4.1.1.3 Power-Supply as Reference
      2. 7.4.2 Current-Output Mode
      3. 7.4.3 比较器模式
        1. 7.4.3.1 可编程迟滞比较器
        2. 7.4.3.2 Programmable Window Comparator
      4. 7.4.4 故障转储模式
      5. 7.4.5 应用特定模式
        1. 7.4.5.1 电压裕量和调节
          1. 7.4.5.1.1 高阻抗输出和 PROTECT 输入
          2. 7.4.5.1.2 Programmable Slew-Rate Control
          3. 7.4.5.1.3 PMBus Compatibility Mode
        2. 7.4.5.2 函数生成
          1. 7.4.5.2.1 Triangular Waveform Generation
          2. 7.4.5.2.2 Sawtooth Waveform Generation
          3. 7.4.5.2.3 Sine Waveform Generation
      6. 7.4.6 器件复位和故障管理
        1. 7.4.6.1 上电复位 (POR)
        2. 7.4.6.2 External Reset
        3. 7.4.6.3 Register-Map Lock
        4. 7.4.6.4 NVM 循环冗余校验 (CRC)
          1. 7.4.6.4.1 NVM-CRC-FAIL-USER 位
          2. 7.4.6.4.2 NVM-CRC-FAIL-INT 位
      7. 7.4.7 Power-Down Mode
    5. 7.5 编程
      1. 7.5.1 SPI 编程模式
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S 模式协议
        2. 7.5.2.2 I2C 更新序列
          1. 7.5.2.2.1 地址字节
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C 读取序列
      3. 7.5.3 通用输入/输出 (GPIO) 模式
    6. 7.6 Register Map
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-X-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
      3. 7.6.3  DAC-X-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
      4. 7.6.4  DAC-X-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0000h]
      5. 7.6.5  DAC-X-IOUT-MISC-CONFIG Register (address = 04h, 0Ah, 10h, 16h) [reset = 0000h]
      6. 7.6.6  DAC-X-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
      7. 7.6.7  DAC-X-FUNC-CONFIG Register (address = 06h, 0Ch, 12h, 18h) [reset = 0000h]
      8. 7.6.8  DAC-X-DATA Register (address = 19h, 1Ah, 1Bh, 1Ch) [reset = 0000h]
      9. 7.6.9  COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
      10. 7.6.10 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      11. 7.6.11 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      12. 7.6.12 GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      13. 7.6.13 CMP-STATUS 寄存器（地址 = 23h）[复位 = 0000h]
      14. 7.6.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
      15. 7.6.15 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
      16. 7.6.16 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      17. 7.6.17 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      18. 7.6.18 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      19. 7.6.19 DAC-X-DATA-8BIT Register (address = 40h, 41h, 42h, 43h) [reset = 0000h]
      20. 7.6.20 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
      21. 7.6.21 PMBUS-PAGE Register [reset = 0300h]
      22. 7.6.22 PMBUS-OP-CMD-X Register [reset = 0000h]
      23. 7.6.23 PMBUS-CML Register [reset = 0000h]
      24. 7.6.24 PMBUS-VERSION 寄存器 [复位 = 2200h]
  8. 8 应用和实现
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 布局
      1. 8.4.1 布局指南
      2. 8.4.2 Layout Example
  9. 9 器件和文档支持
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 商标
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 术语表
  10. 10机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6.7 DAC-X-FUNC-CONFIG Register (address = 06h, 0Ch, 12h, 18h) [reset = 0000h]

PMBus page address = FFh, PMBus register address = D4h, D8h, DCh, E0h

Figure 7-30 DAC-X-FUNC-CONFIG Register (X = 0, 1, 2, 3)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLR-SEL-X SYNC-CONFIG-X BRD-CONFIG-X FUNC-GEN-CONFIG-BLOCK
R/W-0h R/W-0h R/W-0h R/W-000h
Table 7-29 DAC-X-FUNC-CONFIG Register Field Descriptions
Bit Field Type Reset Description
15 CLR-SEL-X R/W 0 0: Clear DAC-X to zero-scale
1: Clear DAC-X to mid-scale
14 SYNC-CONFIG-X R/W 0 0: DAC-X output updates immediately after a write command
1: DAC-X output updates with LDAC pin falling-edge or when the LDAC bit in the COMMON-TRIGGER register is set to 1
13 BRD-CONFIG-X R/W 0 0: Don't update DAC-X with broadcast command
1: Update DAC-X with broadcast command
Table 7-30 Linear-Slew Mode: FUNC-GEN-CONFIG-BLOCK Field Descriptions
Bit Field Type Reset Description
12-11 PHASE-SEL-X R/W 0 00: 0°
01: 120°
10: 240°
11: 90°
10-8 FUNC-CONFIG-X R/W 0 000: Triangular wave
001: Sawtooth wave
010: Inverse sawtooth wave
100: Sine wave
111: Disable function generation
Others: Invalid
7 LOG-SLEW-EN-X R/W 0 0: Enable linear slew
6-4 CODE-STEP-X R/W 0 CODE-STEP for linear slew mode:
000: 1-LSB
001: 2-LSB
010: 3-LSB
011: 4-LSB
100: 6-LSB
101: 8-LSB
110: 16-LSB
111: 32-LSB
3-0 SLEW-RATE-X R/W 0 SLEW-RATE for linear slew mode:
0000: No slew for margin-high and margin-low. Invalid for waveform generation.
0001: 4 µs/step
0010: 8 µs/step
0011: 12 µs/step
0100: 18 µs/step
0101: 27.04 µs/step
0110: 40.48 µs/step
0111: 60.72 µs/step
1000: 91.12 µs/step
1001: 136.72 µs/step
1010: 239.2 µs/step
1011: 418.64 µs/step
1100: 732.56 µs/step
1101: 1282 µs/step
1110: 2563.96 µs/step
1111: 5127.92 µs/step
Table 7-31 Logarithmic-Slew Mode: FUNC-GEN-CONFIG-BLOCK Field Descriptions
Bit Field Type Reset Description
12-11 PHASE-SEL-X R/W 0 00: 0°
01: 120°
10: 240°
11: 90°
10 - 8 FUNC-CONFIG-X R/W 0 000: Triangular wave
001: Sawtooth wave
010: Inverse sawtooth wave
100: Sine wave
111: Disable function generation
Others: Invalid
7 LOG-SLEW-EN-X R/W 0 1: Enable logarithmic slew.
In logarithmic slew mode, the DAC output moves from the DAC-X-MARGIN-LOW code to the DAC-X-MARGIN-HIGH code, or vice versa, in 3.125% steps.
When slewing in the positive direction, the next step is (1 + 0.03125) times the current step.
When slewing in the negative direction, the next step is (1 ‒ 0.03125) times the current step.
When DAC-X-MARGIN-LOW is 0, the slew starts from code 1.
The time interval for each step is defined by RISE-SLEW-X and FALL-SLEW-X.
6-4 RISE-SLEW-X R/W 0 SLEW-RATE for logarithmic slew mode (DAC-X-MARGIN-LOW to DAC-X-MARGIN-HIGH):
000: 4 µs/step
001: 12 µs/step
010: 27.04 µs/step
011: 60.72 µs/step
100: 136.72 µs/step
101: 418.64 µs/step
110: 1282 µs/step
111: 5127.92 µs/step
3-1 FALL-SLEW-X R/W 0 SLEW-RATE for logarithmic slew mode (DAC-X-MARGIN-HIGH to DAC-X-MARGIN-LOW):
000: 4 µs/step
001: 12 µs/step
010: 27.04 µs/step
011: 60.72 µs/step
100: 136.72 µs/step
101: 418.64 µs/step
110: 1282 µs/step
111: 5127.92 µs/step
0 X X 0 Don't care