ZHCSRA2 December   2022 DAC53204W , DAC63204W

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 规格
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Current Output
    7. 6.7  Electrical Characteristics: Comparator Mode
    8. 6.8  Electrical Characteristics: General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 6.15 Timing Requirements: GPIO
    16. 6.16 Timing Diagrams
    17. 6.17 Typical Characteristics: Voltage Output
    18. 6.18 Typical Characteristics: Current Output
    19. 6.19 Typical Characteristics: Comparator
    20. 6.20 Typical Characteristics: General
  7. 7 详细说明
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 特性说明
      1. 7.3.1 智能数模转换器 (DAC) 架构
      2. 7.3.2 数字输入/输出
      3. 7.3.3 Nonvolatile Memory (NVM)
    4. 7.4 器件功能模式
      1. 7.4.1 电压输出模式
        1. 7.4.1.1 电压基准和 DAC 传递函数
          1. 7.4.1.1.1 Internal Reference
          2. 7.4.1.1.2 External Reference
          3. 7.4.1.1.3 Power-Supply as Reference
      2. 7.4.2 Current-Output Mode
      3. 7.4.3 比较器模式
        1. 7.4.3.1 可编程迟滞比较器
        2. 7.4.3.2 Programmable Window Comparator
      4. 7.4.4 故障转储模式
      5. 7.4.5 应用特定模式
        1. 7.4.5.1 电压裕量和调节
          1. 7.4.5.1.1 高阻抗输出和 PROTECT 输入
          2. 7.4.5.1.2 Programmable Slew-Rate Control
          3. 7.4.5.1.3 PMBus Compatibility Mode
        2. 7.4.5.2 函数生成
          1. 7.4.5.2.1 Triangular Waveform Generation
          2. 7.4.5.2.2 Sawtooth Waveform Generation
          3. 7.4.5.2.3 Sine Waveform Generation
      6. 7.4.6 器件复位和故障管理
        1. 7.4.6.1 上电复位 (POR)
        2. 7.4.6.2 External Reset
        3. 7.4.6.3 Register-Map Lock
        4. 7.4.6.4 NVM 循环冗余校验 (CRC)
          1. 7.4.6.4.1 NVM-CRC-FAIL-USER 位
          2. 7.4.6.4.2 NVM-CRC-FAIL-INT 位
      7. 7.4.7 Power-Down Mode
    5. 7.5 编程
      1. 7.5.1 SPI 编程模式
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S 模式协议
        2. 7.5.2.2 I2C 更新序列
          1. 7.5.2.2.1 地址字节
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C 读取序列
      3. 7.5.3 通用输入/输出 (GPIO) 模式
    6. 7.6 Register Map
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-X-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
      3. 7.6.3  DAC-X-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
      4. 7.6.4  DAC-X-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0000h]
      5. 7.6.5  DAC-X-IOUT-MISC-CONFIG Register (address = 04h, 0Ah, 10h, 16h) [reset = 0000h]
      6. 7.6.6  DAC-X-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
      7. 7.6.7  DAC-X-FUNC-CONFIG Register (address = 06h, 0Ch, 12h, 18h) [reset = 0000h]
      8. 7.6.8  DAC-X-DATA Register (address = 19h, 1Ah, 1Bh, 1Ch) [reset = 0000h]
      9. 7.6.9  COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
      10. 7.6.10 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      11. 7.6.11 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      12. 7.6.12 GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      13. 7.6.13 CMP-STATUS 寄存器（地址 = 23h）[复位 = 0000h]
      14. 7.6.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
      15. 7.6.15 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
      16. 7.6.16 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      17. 7.6.17 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      18. 7.6.18 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      19. 7.6.19 DAC-X-DATA-8BIT Register (address = 40h, 41h, 42h, 43h) [reset = 0000h]
      20. 7.6.20 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
      21. 7.6.21 PMBUS-PAGE Register [reset = 0300h]
      22. 7.6.22 PMBUS-OP-CMD-X Register [reset = 0000h]
      23. 7.6.23 PMBUS-CML Register [reset = 0000h]
      24. 7.6.24 PMBUS-VERSION 寄存器 [复位 = 2200h]
  8. 8 应用和实现
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 布局
      1. 8.4.1 布局指南
      2. 8.4.2 Layout Example
  9. 9 器件和文档支持
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 商标
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 术语表
  10. 10机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6 Register Map

Table 7-20 Register Map
REGISTER(1)(2) MOST SIGNIFICANT DATA BYTE (MSDB) LEAST SIGNIFICANT DATA BYTE (LSDB)
BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
NOP NOP
DAC-X-MARGIN-HIGH DAC-X-MARGIN-HIGH X
DAC-X-MARGIN-LOW DAC-X-MARGIN-LOW X
DAC-X-VOUT-CMP-CONFIG X VOUT-GAIN-X X CMP-X-OD-EN CMP-X-OUT-EN CMP-X-HIZ-IN-DIS CMP-X-INV-EN CMP-X-EN
DAC-X-IOUT-MISC-CONFIG X IOUT-X-RANGE X
DAC-X-CMP-MODE-CONFIG X CMP-X-MODE X
DAC-X-FUNC-CONFIG CLR-SEL-X SYNC-CONFIG-X BRD-CONFIG-X FUNC-GEN-CONFIG-BLOCK-X
DAC-X-DATA DAC-X-DATA X
COMMON-CONFIG WIN-LATCH-EN DEV-LOCK EE-READ-ADDR EN-INT-REF VOUT-PDN-3 IOUT-PDN-3 VOUT-PDN-2 IOUT-PDN-2 VOUT-PDN-1 IOUT-PDN-1 VOUT-PDN-0 IOUT-PDN-0
COMMON-TRIGGER DEV-UNLOCK RESET LDAC CLR X FAULT-DUMP PROTECT READ-ONE-TRIG NVM-PROG NVM-RELOAD
COMMON-DAC-TRIG RST-CMP-FLAG-0 TRIG-MAR-LO-0 TRIG-MAR-HI-0 START-FUNC-0 RST-CMP-FLAG-1 TRIG-MAR-LO-1 TRIG-MAR-HI-1 START-FUNC-1 RST-CMP-FLAG-2 TRIG-MAR-LO-2 TRIG-MAR-HI-2 START-FUNC-2 RST-CMP-FLAG-3 TRIG-MAR-LO-3 TRIG-MAR-HI-3 START-FUNC-3
GENERAL-STATUS NVM-CRC-FAIL-INT NVM-CRC-FAIL-USER X DAC-BUSY-3 DAC-BUSY-2 DAC-BUSY-1 DAC-BUSY-0 NVM-BUSY DEVICE-ID
CMP-STATUS X PROTECT-FLAG WIN-CMP-3 WIN-CMP-2 WIN-CMP-1 WIN-CMP-0 CMP-FLAG-3 CMP-FLAG-2 CMP-FLAG-1 CMP-FLAG-0
GPIO-CONFIG GF-EN X GPO-EN GPO-CONFIG GPI-CH-SEL GPI-CONFIG GPI-EN
DEVICE-MODE-CONFIG RESERVED DIS-MODE-IN RESERVED PROTECT-CONFIG RESERVED X
INTERFACE-CONFIG X TIMEOUT-EN X EN-PMBUS X FSDO-EN X SDO-EN
SRAM-CONFIG X SRAM-ADDR
SRAM-DATA SRAM-DATA
DAC-X-DATA-8BIT DAC-X-DATA-8BIT X
BRDCAST-DATA BRDCAST-DATA X
PMBUS-PAGE PMBUS-PAGE NA
PMBUS-OP-CMD PMBUS-OPERATION-CMD-X NA
PMBUS-CML X CML X NA
PMBUS-VERSION PMBUS-VERSON NA
(1) The highlighted gray cells indicate the register bits or fields that are stored in the NVM.
(2) X = Don't care.
Table 7-21 Register Names
I2C/SPI ADDRESS PMBUS PAGE ADDR PMBUS REGISTER ADDR REGISTER NAME SECTION
00h FFh D0h NOP Section 7.6.1
01h 00h 25h DAC-0-MARGIN-HIGH Section 7.6.2
02h 00h 26h DAC-0-MARGIN-LOW Section 7.6.3
03h FFh D1h DAC-0-VOUT-CMP-CONFIG Section 7.6.4
04h FFh D2h DAC-0-IOUT-MISC-CONFIG Section 7.6.5
05h FFh D3h DAC-0-CMP-MODE-CONFIG Section 7.6.6
06h FFh D4h DAC-0-FUNC-CONFIG Section 7.6.7
07h 01h 25h DAC-1-MARGIN-HIGH Section 7.6.2
08h 01h 26h DAC-1-MARGIN-LOW Section 7.6.3
09h FFh D5h DAC-1-VOUT-CMP-CONFIG Section 7.6.4
0Ah FFh D6h DAC-1-IOUT-MISC-CONFIG Section 7.6.5
0Bh FFh D7h DAC-1-CMP-MODE-CONFIG Section 7.6.6
0Ch FFh D8h DAC-1-FUNC-CONFIG Section 7.6.7
0Dh 02h 25h DAC-2-MARGIN-HIGH Section 7.6.2
0Eh 02h 26h DAC-2-MARGIN-LOW Section 7.6.3
0Fh FFh D9h DAC-2-VOUT-CMP-CONFIG Section 7.6.4
10h FFh DAh DAC-2-IOUT-MISC-CONFIG Section 7.6.5
11h FFh DBh DAC-2-CMP-MODE-CONFIG Section 7.6.6
12h FFh DCh DAC-2-FUNC-CONFIG Section 7.6.7
13h 03h 25h DAC-3-MARGIN-HIGH Section 7.6.2
14h 03h 26h DAC-3-MARGIN-LOW Section 7.6.3
15h FFh DDh DAC-3-VOUT-CMP-CONFIG Section 7.6.4
16h FFh DEh DAC-3-IOUT-MISC-CONFIG Section 7.6.5
17h FFh DFh DAC-3-CMP-MODE-CONFIG Section 7.6.6
18h FFh E0h DAC-3-FUNC-CONFIG Section 7.6.7
19h 00h 21h DAC-0-DATA Section 7.6.8
1Ah 01h 21h DAC-1-DATA Section 7.6.8
1Bh 02h 21h DAC-2-DATA Section 7.6.8
1Ch 03h 21h DAC-3-DATA Section 7.6.8
1Fh FFh E3h COMMON-CONFIG Section 7.6.9
20h FFh E4h COMMON-TRIGGER Section 7.6.10
21h FFh E5h COMMON-DAC-TRIG Section 7.6.11
22h FFh E6h GENERAL-STATUS Section 7.6.12
23h FFh E7h CMP-STATUS Section 7.6.13
24h FFh E8h GPIO-CONFIG Section 7.6.14
25h FFh E9h DEVICE-MODE-CONFIG Section 7.6.15
26h FFh EAh INTERFACE-CONFIG Section 7.6.16
2Bh FFh EFh SRAM-CONFIG Section 7.6.17
2Ch FFh F0h SRAM-DATA Section 7.6.18
40h NA NA DAC-0-DATA-8BIT Section 7.6.19
41h NA NA DAC-1-DATA-8BIT Section 7.6.19
42h NA NA DAC-2-DATA-8BIT Section 7.6.19
43h NA NA DAC-3-DATA-8BIT Section 7.6.19
50h FFh F1h BRDCAST-DATA Section 7.6.20
NA All pages 00h PMBUS-PAGE Section 7.6.21
NA 00h 01h PMBIS-OP-CMD-0 Section 7.6.22
NA 01h 01h PMBUS-OP-CMD-1 Section 7.6.22
NA 02h 01h PMBUS-OP-CMD-2 Section 7.6.22
NA 03h 01h PMBUS-OP-CMD-3 Section 7.6.22
NA All pages 78h PMBUS-CML Section 7.6.23
NA All pages 98h PMBUS-VERSION Section 7.6.24
Table 7-22 Access Type Codes
Access Type Code Description
X X Don't care
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value