ZHCSAY0D March   2013  – April 2015 CSD87588N

PRODUCTION DATA.  

  1. 1特性
  2. 2应用范围
  3. 3说明
  4. 4修订历史记录
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Power Block Performance
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Power Loss Curves
      2. 6.1.2 Safe Operating Curves (SOA)
      3. 6.1.3 Normalized Curves
      4. 6.1.4 Calculating Power Loss and SOA
        1. 6.1.4.1 Design Example
        2. 6.1.4.2 Calculating Power Loss
        3. 6.1.4.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Electrical Performance
      2. 7.1.2 Thermal Performance
    2. 7.2 Layout Example
  8. 8器件和文档支持
    1. 8.1 商标
    2. 8.2 静电放电警告
    3. 8.3 术语表
  9. 9机械、封装和可订购信息
    1. 9.1 CSD87588N 封装尺寸
    2. 9.2 焊盘布局建议
    3. 9.3 模板建议 (100µm)
    4. 9.4 模板建议 (125µm)
    5. 9.5 引脚图
    6. 9.6 CSD87588N 压纹载带尺寸

封装选项

机械数据 (封装 | 引脚)
  • MPA|5
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Layout

7.1 Layout Guidelines

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. The following sections provide a brief description on how to address each parameter.

7.1.1 Electrical Performance

The CSD87588N has the ability to switch voltages at rates greater than 10 kV/µs. Take special care with the PCB layout design and placement of the input capacitors, inductor, and output capacitors.

  • The placement of the input capacitors relative to VIN and PGND pins of CSD87588N device should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 29). The example in Figure 29 uses 1 x 10 nF 0402 25 V and 4 x 10 μF 1206 25 V ceramic capacitors (TDK part number C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power Stage C21, C5, C8, C19, and C18 should follow in order.
  • The switching node of the output inductor should be placed relatively close to the Power Block II CSD87588N VSW pins. Minimizing the VSW node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level. See Figure 29. (1)
(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla

7.1.2 Thermal Performance

The CSD87588N has the ability to utilize the PGND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that wicks down the via barrel:

  • Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
  • Use the smallest drill size allowed in your design. The example in Figure 29 uses vias with a 10 mil drill hole and a 16 mil capture pad.
  • Tent the opposite side of the via with solder-mask.

The number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities.

7.2 Layout Example

CSD87588N Thermal_Performance_Image.pngFigure 29. Recommended PCB Layout (Top Down View)