ZHCSOP0B October   2001  – January 2022 CDCVF25081

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • PW|16
  • D|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

Figure 5-1 D or PW Package16-Pin SOIC or TSSOPTop View
Table 5-1 Pin Functions
PIN I/O TYPE(1) DESCRIPTION
NAME NO.
INPUT CLOCK
CLKIN 1 I Clock input. CLKIN must have a fixed frequency and phase in order for the PLL to acquire lock. Once the circuit is powered up and a valid signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to CLKIN.
INPUT SELECT
S1, S2 9, 8 I Input Selection. Selects input port. (See Table 8-2.)
FEEDBACK
FBIN 16 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be wired to one of the outputs to complete the feedback loop of the internal PLL. The integrated PLL synchronizes the FBIN and output signal so there is nominally zero-delay from input clock to output clock.
OUTPUT CLOCKS
1Y0 2 O Bank 1 Y0 clock output with an integrated 25-Ω series-damping resistor.
1Y1 3 O Bank 1 Y1 clock output with an integrated 25-Ω series-damping resistor.
1Y2 14 O Bank 1 Y2 clock output with an integrated 25-Ω series-damping resistor.
1Y3 15 O Bank 1 Y3 clock output with an integrated 25-Ω series-damping resistor.
2Y0 6 O Bank 2 Y0 clock output with an integrated 25-Ω series-damping resistor.
2Y1 7 O Bank 2 Y1 clock output with an integrated 25-Ω series-damping resistor.
2Y2 10 O Bank 2 Y2 clock output with an integrated 25-Ω series-damping resistor.
2Y3 11 O Bank 2 Y3 clock output with an integrated 25-Ω series-damping resistor.
SUPPLY VOLTAGE AND GROUND
VDD 4, 13 P 3.3V power supply for output channels and core voltage.
GND 5, 12 G Ground. Connect ground pad to system ground.
(1) The definitions below define the I/O type for each pin.
  • I = Input
  • O = Output
  • P = Power Supply
  • G = Ground