ZHCSOP0B October 2001 – January 2022 CDCVF25081
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |
|---|---|---|---|---|---|---|
| t(lock) | PLL lock time | f = 100 MHz | 10 | µs | ||
| t(phoffset) | Phase offset (CLKIN to FBIN) | f = 8 MHz to 66 MHz, Vth = VDD/2 (3) | –200 | 200 | ps | |
| f = 66 MHz to 200 MHz, Vth = VDD/2 (3) | –150 | 150 | ||||
| tPLH | Low-to-high level output propagation delay | S2 = High, S1 = Low (PLL bypass), f = 1 MHz, CL = 25 pF | 2.5 | 6 | ns | |
| tPHL | High-to-low level output propagation delay | 2.5 | 6 | |||
| tsk(o) | Output skew (Yn to Yn) (2) | 150 | ps | |||
| tsk(pp) | Part-to-part skew | S2 = high, S1 = high (PLL mode) | 600 | ps | ||
| S2 = high, S1 = low (PLL bypass) | 700 | |||||
| tjit(cc) | Jitter (cycle-to-cycle) | f = 66 MHz to 200 MHz, CL = 15 pF | ±100 | ps | ||
| f = 66 MHz to 100 MHz,
CL = 25 pF, f = 8 MHz to 66 MHz (see Figure 6-2) | ±150 | |||||
| odc | Output duty cycle | f = 8 MHz to 200 MHz | 43% | 57% | ||
| tsk(p) | Pulse skew | S2 = High, S1 = low (PLL bypass), f = 1 MHz, CL = 25 pF | 0.7 | ns | ||
| tRISE | Rise time rate | CL = 15 pF, See Figure 7-4 | 0.8 | 3.3 | V/ns | |
| CL = 25 pF, See Figure 7-4 | 0.5 | 2 | ||||
| tFALL | Fall time rate | CL = 15 pF, See Figure 7-4 | 0.8 | 3.3 | V/ns | |
| CL = 25 pF, See Figure 7-4 | 0.5 | 2 | ||||