ZHCSOK7B March   2020  – May 2021 CC3130

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
      1.      12
    4. 7.4 Connections for Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Current Consumption Summary
    6. 8.6  TX Power Control
    7. 8.7  Brownout and Blackout Conditions
      1. 8.7.1 Brownout and Blackout Voltage Levels
    8. 8.8  Electrical Characteristics for DIO Pins
      1. 8.8.1 Electrical Characteristics: DIO Pins Except 52 and 53
      2. 8.8.2 Electrical Characteristics: DIO Pins 52 and 53
    9. 8.9  Electrical Characteristics for Pin Internal Pullup and Pulldown
    10. 8.10 WLAN Receiver Characteristics
      1.      28
    11. 8.11 WLAN Transmitter Characteristics
      1.      30
    12. 8.12 WLAN Transmitter Out-of-Band Emissions
      1. 8.12.1 WLAN 2.4 GHz Filter Requirements
    13. 8.13 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
    14. 8.14 Thermal Resistance Characteristics for RGK Package
    15. 8.15 Timing and Switching Characteristics
      1. 8.15.1 Power Supply Sequencing
      2. 8.15.2 Device Reset
      3. 8.15.3 Reset Timing
        1. 8.15.3.1 nRESET (32-kHz Crystal)
        2. 8.15.3.2 First-Time Power-Up and Reset Removal Timing Requirements (32-kHz Crystal)
        3. 8.15.3.3 nRESET (External 32-kHz Crystal)
          1. 8.15.3.3.1 First-Time Power-Up and Reset Removal Timing Requirements (External 32-kHz Crystal)
      4. 8.15.4 Wakeup From HIBERNATE Mode
        1. 8.15.4.1 nHIB Timing Requirements
      5. 8.15.5 Clock Specifications
        1. 8.15.5.1 Slow Clock Using Internal Oscillator
          1. 8.15.5.1.1 RTC Crystal Requirements
        2. 8.15.5.2 Slow Clock Using an External Clock
          1. 8.15.5.2.1 External RTC Digital Clock Requirements
        3. 8.15.5.3 Fast Clock (Fref) Using an External Crystal
          1. 8.15.5.3.1 WLAN Fast-Clock Crystal Requirements
        4. 8.15.5.4 Fast Clock (Fref) Using an External Oscillator
          1. 8.15.5.4.1 External Fref Clock Requirements (–40°C to +85°C)
      6. 8.15.6 Interfaces
        1. 8.15.6.1 Host SPI Interface Timing
          1. 8.15.6.1.1 Host SPI Interface Timing Parameters
        2. 8.15.6.2 Flash SPI Interface Timing
          1. 8.15.6.2.1 Flash SPI Interface Timing Parameters
        3. 8.15.6.3 DIO Interface Timing
          1. 8.15.6.3.1 DIO Output Transition Time Parameters (Vsupply = 3.3 V)
            1. 8.15.6.3.1.1 DIO Output Transition Times (Vsupply = 3.3 V) (1)
          2. 8.15.6.3.2 DIO Input Transition Time Parameters
            1. 8.15.6.3.2.1 DIO Input Transition Time Parameters
    16. 8.16 External Interfaces
      1. 8.16.1 SPI Flash Interface
      2. 8.16.2 SPI Host Interface
      3. 8.16.3 Host UART Interface
        1. 8.16.3.1 5-Wire UART Topology
        2. 8.16.3.2 4-Wire UART Topology
        3. 8.16.3.3 3-Wire UART Topology
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Device Features
      1. 9.2.1 WLAN
      2. 9.2.2 Network Stack
      3. 9.2.3 Security
      4. 9.2.4 Host Interface and Driver
      5. 9.2.5 System
    3. 9.3 Power-Management Subsystem
      1. 9.3.1 VBAT Wide-Voltage Connection
    4. 9.4 Low-Power Operating Modes
      1. 9.4.1 Low-Power Deep Sleep
      2. 9.4.2 Hibernate
      3. 9.4.3 Shutdown
    5. 9.5 Memory
      1. 9.5.1 External Memory Requirements
    6. 9.6 Restoring Factory Default Configuration
    7. 9.7 Hostless Mode
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 BLE/2.4 GHz Radio Coexistence
      2. 10.1.2 Antenna Selection
      3. 10.1.3 Typical Application
    2. 10.2 PCB Layout Guidelines
      1. 10.2.1 General PCB Guidelines
      2. 10.2.2 Power Layout and Routing
        1. 10.2.2.1 Design Considerations
      3. 10.2.3 Clock Interface Guidelines
      4. 10.2.4 Digital Input and Output Guidelines
      5. 10.2.5 RF Interface Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Tools and Software
    2. 11.2 Firmware Updates
    3. 11.3 Device Nomenclature
    4. 11.4 Documentation Support
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10.2.2.1 Design Considerations

The following design guidelines must be followed when laying out the CC3130 device:

  • Ground returns of the input decoupling capacitors (C11, C13, and C19) should be routed on Layer 2 using thick traces to isolate the RF ground from the noisy supply ground. This step is also required to meet the IEEE spectral mask specifications.
  • Maintain the thickness of power traces to be greater than 12 mils. Take special consideration for power amplifier supply lines (pin 33, 40, 41, and 42), and all input supply pins (pin 37, 39, and 44).
  • Ensure the shortest grounding loop for the PLL supply decoupling capacitor (pin 24).
  • Place all decoupling capacitors as close to the respective pins as possible.
  • Power budget—the CC3130 device can consume up to 450 mA for 3.3 V, 670 mA for 2.1 V, for
    24 ms during the calibration cycle.
  • Ensure the power supply is designed to source this current without any issues. The complete calibration (TX and RX) can take up to 17 mJ of energy from the battery over a time of 24 ms.
  • The CC3130 device contains many high-current input pins. Ensure the trace feeding these pins can handle the following currents:
    • VIN_DCDC_PA input (pin 39) maximum 1 A
    • VIN_DCDC_ANA input (pin 37) maximum 600 mA
    • VIN_DCDC_DIG input (pin 44) maximum 500 mA
    • DCDC_PA_SW_P (pin 40) and DCDC_PA_SW_N (pin 41) switching nodes maximum 1 A
    • DCDC_PA_OUT output node (pin 42) maximum 1 A
    • DCDC_ANA_SW switching node (pin 38) maximum 600 mA
    • DCDC_DIG_SW switching node (pin 43) maximum 500 mA
    • VDD_PA_IN supply (pin 33) maximum 500 mA
GUID-BB3B0A06-A6A3-4C93-BD4A-BB00B7629013-low.pngFigure 10-6 Ground Returns for Input Capacitors