ZHCSOK7B March   2020  – May 2021 CC3130

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
      1.      12
    4. 7.4 Connections for Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Current Consumption Summary
    6. 8.6  TX Power Control
    7. 8.7  Brownout and Blackout Conditions
      1. 8.7.1 Brownout and Blackout Voltage Levels
    8. 8.8  Electrical Characteristics for DIO Pins
      1. 8.8.1 Electrical Characteristics: DIO Pins Except 52 and 53
      2. 8.8.2 Electrical Characteristics: DIO Pins 52 and 53
    9. 8.9  Electrical Characteristics for Pin Internal Pullup and Pulldown
    10. 8.10 WLAN Receiver Characteristics
      1.      28
    11. 8.11 WLAN Transmitter Characteristics
      1.      30
    12. 8.12 WLAN Transmitter Out-of-Band Emissions
      1. 8.12.1 WLAN 2.4 GHz Filter Requirements
    13. 8.13 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
    14. 8.14 Thermal Resistance Characteristics for RGK Package
    15. 8.15 Timing and Switching Characteristics
      1. 8.15.1 Power Supply Sequencing
      2. 8.15.2 Device Reset
      3. 8.15.3 Reset Timing
        1. 8.15.3.1 nRESET (32-kHz Crystal)
        2. 8.15.3.2 First-Time Power-Up and Reset Removal Timing Requirements (32-kHz Crystal)
        3. 8.15.3.3 nRESET (External 32-kHz Crystal)
          1. 8.15.3.3.1 First-Time Power-Up and Reset Removal Timing Requirements (External 32-kHz Crystal)
      4. 8.15.4 Wakeup From HIBERNATE Mode
        1. 8.15.4.1 nHIB Timing Requirements
      5. 8.15.5 Clock Specifications
        1. 8.15.5.1 Slow Clock Using Internal Oscillator
          1. 8.15.5.1.1 RTC Crystal Requirements
        2. 8.15.5.2 Slow Clock Using an External Clock
          1. 8.15.5.2.1 External RTC Digital Clock Requirements
        3. 8.15.5.3 Fast Clock (Fref) Using an External Crystal
          1. 8.15.5.3.1 WLAN Fast-Clock Crystal Requirements
        4. 8.15.5.4 Fast Clock (Fref) Using an External Oscillator
          1. 8.15.5.4.1 External Fref Clock Requirements (–40°C to +85°C)
      6. 8.15.6 Interfaces
        1. 8.15.6.1 Host SPI Interface Timing
          1. 8.15.6.1.1 Host SPI Interface Timing Parameters
        2. 8.15.6.2 Flash SPI Interface Timing
          1. 8.15.6.2.1 Flash SPI Interface Timing Parameters
        3. 8.15.6.3 DIO Interface Timing
          1. 8.15.6.3.1 DIO Output Transition Time Parameters (Vsupply = 3.3 V)
            1. 8.15.6.3.1.1 DIO Output Transition Times (Vsupply = 3.3 V) (1)
          2. 8.15.6.3.2 DIO Input Transition Time Parameters
            1. 8.15.6.3.2.1 DIO Input Transition Time Parameters
    16. 8.16 External Interfaces
      1. 8.16.1 SPI Flash Interface
      2. 8.16.2 SPI Host Interface
      3. 8.16.3 Host UART Interface
        1. 8.16.3.1 5-Wire UART Topology
        2. 8.16.3.2 4-Wire UART Topology
        3. 8.16.3.3 3-Wire UART Topology
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Device Features
      1. 9.2.1 WLAN
      2. 9.2.2 Network Stack
      3. 9.2.3 Security
      4. 9.2.4 Host Interface and Driver
      5. 9.2.5 System
    3. 9.3 Power-Management Subsystem
      1. 9.3.1 VBAT Wide-Voltage Connection
    4. 9.4 Low-Power Operating Modes
      1. 9.4.1 Low-Power Deep Sleep
      2. 9.4.2 Hibernate
      3. 9.4.3 Shutdown
    5. 9.5 Memory
      1. 9.5.1 External Memory Requirements
    6. 9.6 Restoring Factory Default Configuration
    7. 9.7 Hostless Mode
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 BLE/2.4 GHz Radio Coexistence
      2. 10.1.2 Antenna Selection
      3. 10.1.3 Typical Application
    2. 10.2 PCB Layout Guidelines
      1. 10.2.1 General PCB Guidelines
      2. 10.2.2 Power Layout and Routing
        1. 10.2.2.1 Design Considerations
      3. 10.2.3 Clock Interface Guidelines
      4. 10.2.4 Digital Input and Output Guidelines
      5. 10.2.5 RF Interface Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Tools and Software
    2. 11.2 Firmware Updates
    3. 11.3 Device Nomenclature
    4. 11.4 Documentation Support
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.2 Pin Attributes

Table 7-1 describes the CC3130 pins.

Note:

Digital IOs on the CC3130 device refer to hostless mode, BLE/2.4 GHz coexistence, and antenna select IOs, not general-purpose IOs.

If an external device drives a positive voltage to signal pads when the CC3130 device is not powered, DC current is drawn from the other device. If the drive strength of the external device is adequate, an unintentional wakeup and boot of the CC3130 device can occur. To prevent current draw, TI recommends one of the following:

  • All devices interfaced to the CC3130 device must be powered from the same power rail as the CC3130 device.
  • Use level shifters between the CC3130 device and any external devices fed from other independent rails.
  • The nRESET pin of the CC3130 device must be held low until the VBAT supply to the device is driven and stable.
Table 7-1 Pin Description and Attributes
PINDEFAULT FUNCTIONDIGITAL I/OSTATE AT RESET AND HIBERNATEI/O TYPE(1)DESCRIPTION
PAD_
CONFIG		HOSTLESS MODEBLE COEX
CC_COEX_
OUT		CC_COEX_
IN
1DIO1010YYY–I/ODigital input or output
2nHIB11---Hi-ZIHibernate signal input to the NWP subsystem (active low). This is connected to the MCU GPIO. If the GPIO from the MCU can float while the MCU enters low power, consider adding a pullup resistor on the board to avoid floating.
3DIO1212YYY–ODigital input or output
4DIO1313YYY––Digital input or output
5HOST_SPI_CLK14---Hi-ZIHost interface SPI clock
6HOST_SPI_MOSI15---Hi-ZIHost interface SPI data input
7HOST_SPI_MISO16---Hi-ZOHost interface SPI data output
8HOST_SPI_nCS17---Hi-ZIHost interface SPI chip select (active low)
9VDD_DIG1-N/AN/AN/AHi-ZPowerDigital core supply (1.2 V)
10VIN_IO1-N/AN/AN/AHi-ZPowerI/O supply
11FLASH_SPI_CLK-N/AN/AN/AHi-ZOSerial Flash interface: SPI clock
12FLASH_SPI_MOSI-N/AN/AN/AHi-ZOSerial Flash interface: SPI data out
13FLASH _SPI_MISO-N/AN/AN/AHi-ZISerial Flash interface: SPI data in (active high)
14FLASH _SPI_CS-N/AN/AN/AHi-ZOSerial Flash interface: SPI chip select (active low)
15HOST_INTR22---Hi-ZOInterrupt output (active high)
16DIO2323YYYHi-ZDigital input or output
17DIO2424YYYHi-ZDigital input or output
18DIO2840YYY––Digital input or output
19Reserved28---Hi-Z–Connect a 100-kΩ pulldown resistor to ground.
20DIO2929YYYHi-ZDigital input or output
21SOP2/TCXO_EN(2)25Y(3)Y-Hi-ZOControls restore to default mode. Enable signal for external TCXO. Add a 10-kΩ pulldown resistor to ground.
22WLAN_XTAL_N-N/AN/AN/AHi-ZAnalogConnect the WLAN 40-MHz crystal here.
23WLAN_XTAL_P-N/AN/AN/AHi-ZAnalogConnect the WLAN 40-MHz crystal here.
24VDD_PLL-N/AN/AN/AHi-ZPowerInternal PLL power supply (1.4 V nominal)
25LDO_IN2-N/AN/AN/AHi-ZPowerInput to internal LDO
26NC-N/AN/AN/A––No Connect
27NC-N/AN/AN/A––No Connect
28NC-N/AN/AN/A––No Connect
29

ANTSEL1(4)

-N/AN/AN/AHi-ZOReserved for future use
30ANTSEL2(4)-N/AN/AN/AHi-ZOReserved for future use
31RF_BG-N/AN/AN/AHi-ZRF2.4 GHz RF TX, RX
32nRESET-N/AN/AN/AHi-ZIRESET input for the device. Active low input. Use RC circuit (100 kΩ || 0.01 µF) for power on reset (POR).
33VDD_PA_IN-N/AN/AN/AHi-ZPowerPower supply for the RF power amplifier (PA)
34SOP1-N/AN/AN/AHi-Z–SOP[2:0] used for factory restore. Add 100-kΩ pulldown to ground. See Section 9.6. SOP1 used for 5 GHz switch control
35SOP0-N/AN/AN/AHi-Z–SOP[2:0] used for factory restore. Add 100-kΩ pulldown to ground. See Section 9.6. SOP0 used for 5GHz switch control
36LDO_IN1-N/AN/AN/AHi-ZPowerInput to internal LDO
37VIN_DCDC_ANA-N/AN/AN/AHi-ZPowerPower supply for the DC/DC converter for analog section
38DCDC_ANA_SW-N/AN/AN/AHi-ZPowerAnalog DC/DC converter switch output
39VIN_DCDC_PA-N/AN/AN/AHi-ZPowerPA DC/DC converter input supply
40DCDC_PA_SW_P-N/AN/AN/AHi-ZPowerPA DC/DC converter switch output +ve
41DCDC_PA_SW_N-N/AN/AN/AHi-ZPowerPA DC/DC converter switch output –ve
42DCDC_PA_OUT-N/AN/AN/AHi-ZPowerPA DC/DC converter output. Connect the output capacitor for DC/DC here.
43DCDC_DIG_SW-N/AN/AN/AHi-ZPowerDigital DC/DC converter switch output
44VIN_DCDC_DIG-N/AN/AN/AHi-ZPowerPower supply input for the digital DC/DC converter
45DIO3131YYYHi-Z–Network Scripter I/O
46DCDC_ANA2_SW_N-N/AN/AN/AHi-ZPowerAnalog2 DC/DC converter switch output –ve
47VDD_ANA2-N/AN/AN/AHi-ZPowerAnalog2 power supply input
48VDD_ANA1-N/AN/AN/AHi-ZPowerAnalog1 power supply input
49VDD_RAM-N/AN/AN/AHi-ZPowerPower supply for the internal RAM
50UART1_nRTS0---Hi-ZOUART host interface (active low)
51RTC_XTAL_P-N/AN/AN/AHi-ZAnalog32.768-kHz XTAL_P or external CMOS level clock input
52RTC_XTAL_N32YYYHi-ZAnalog32.768-kHz XTAL_N or 100-kΩ external pullup for external clock
53DIO3030YYYHi-Z–Network Scripter I/O
54VIN_IO2N/AN/AN/AHi-ZPowerI/O power supply. Same as battery voltage.
55UART1_TX1---Hi-ZOUART host interface. Connect to test point on prototype for Flash programming.
56VDD_DIG2-N/AHi-ZPowerDigital power supply (1.2 V)
57UART1_RX2---Hi-ZIUART host interface; connect to test point on prototype for Flash programming.
58TEST_583YYYHi-ZOTest signal; connect to an external test point.
59TEST_604YYYHi-ZOTest signal; connect to an external test point.
60TEST_605YYYHi-ZOTest signal; connect to an external test point.
61UART1_nCTS6---Hi-ZIUART host interface (active low)
62TEST_627---Hi-ZOTest signal; connect to an external test point.
63DIO88YYYHi-ZDigital input or output
64DIO99YYYHi-Z–Digital input or output
65GND-N/AN/AN/A–PowerGround tab used as thermal and electrical ground
(1) I = input
O = output
RF = radio frequency
I/O = bidirectional
(2) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(3) Output Only
(4)

This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3130x device between two antennas. These pins must not be used for other functionalities.