ZHCSKQ3D january   2020  – july 2023 CC2642R-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Functional Block Diagram
  6. 5 Revision History
  7. 6 Device Comparison
  8. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram – RTC and RGZ Package (Top View)
    2. 7.2 Signal Descriptions
    3. 7.3 Connections for Unused Pins and Modules
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Power Supply and Modules
    5. 8.5  Power Consumption - Power Modes
    6. 8.6  Power Consumption - Radio Modes
    7. 8.7  Nonvolatile (Flash) Memory Characteristics
    8. 8.8  Thermal Resistance Characteristics
    9. 8.9  Bluetooth Low Energy Receive (RX)
    10. 8.10 Bluetooth Low Energy - Transmit (TX)
    11. 8.11 Timing and Switching Characteristics
      1. 8.11.1 Reset Timing
      2. 8.11.2 Wakeup Timing
      3. 8.11.3 Clock Specifications
        1. 8.11.3.1 48 MHz Crystal Oscillator (XOSC_HF)
        2. 8.11.3.2 48 MHz RC Oscillator (RCOSC_HF)
        3. 8.11.3.3 2 MHz RC Oscillator (RCOSC_MF)
        4. 8.11.3.4 32.768 kHz Crystal Oscillator (XOSC_LF)
        5. 8.11.3.5 32 kHz RC Oscillator (RCOSC_LF)
      4. 8.11.4 Synchronous Serial Interface (SSI) Characteristics
        1. 8.11.4.1 Synchronous Serial Interface (SSI) Characteristics
        2.       34
      5. 8.11.5 UART
        1. 8.11.5.1 UART Characteristics
    12. 8.12 Peripheral Characteristics
      1. 8.12.1 ADC
        1.       Analog-to-Digital Converter (ADC) Characteristics
      2. 8.12.2 DAC
        1. 8.12.2.1 Digital-to-Analog Converter (DAC) Characteristics
      3. 8.12.3 Temperature and Battery Monitor
        1. 8.12.3.1 Temperature Sensor
        2. 8.12.3.2 Battery Monitor
      4. 8.12.4 Comparators
        1. 8.12.4.1 Continuous Time Comparator
        2. 8.12.4.2 Low-Power Clocked Comparator
      5. 8.12.5 Current Source
        1. 8.12.5.1 Programmable Current Source
      6. 8.12.6 GPIO
        1. 8.12.6.1 GPIO DC Characteristics
    13. 8.13 Typical Characteristics
      1. 8.13.1 MCU Current
      2. 8.13.2 RX Current
      3. 8.13.3 TX Current
      4. 8.13.4 RX Performance
      5. 8.13.5 TX Performance
      6. 8.13.6 ADC Performance
  10. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  System CPU
    3. 9.3  Radio (RF Core)
      1. 9.3.1 Bluetooth 5 low energy
    4. 9.4  Memory
    5. 9.5  Sensor Controller
    6. 9.6  Cryptography
    7. 9.7  Timers
    8. 9.8  Serial Peripherals and I/O
    9. 9.9  Battery and Temperature Monitor
    10. 9.10 µDMA
    11. 9.11 Debug
    12. 9.12 Power Management
    13. 9.13 Clock Systems
    14. 9.14 Network Processor
  11. 10Application, Implementation, and Layout
    1. 10.1 Reference Designs
    2. 10.2 Junction Temperature Calculation
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
      1. 11.2.1 SimpleLink™ Microcontroller Platform
    3. 11.3 Documentation Support
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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Analog-to-Digital Converter (ADC) Characteristics

Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range 0 VDDS V
Resolution 12 Bits
Sample rate 200 kSamples/s
Offset Internal 4.3 V equivalent reference(2) –0.24 LSB
Gain error Internal 4.3 V equivalent reference(2) 7.14 LSB
DNL(4) Differential nonlinearity >–1 LSB
INL Integral nonlinearity ±4 LSB
ENOB Effective number of bits Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone		 9.8 Bits
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone, DC/DC enabled		 9.8
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone  10.1
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone		 11.1
Internal reference, voltage scaling disabled,
14-bit mode, 200 kSamples/s, 600 Hz input tone (5)		 11.3
Internal reference, voltage scaling disabled,
15-bit mode, 200 kSamples/s, 150 Hz input tone (5)		 11.6
THD Total harmonic distortion Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone 		 –65 dB
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone  –70
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone 		 –72
SINAD,
SNDR		 Signal-to-noise
and
distortion ratio		 Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone		 60 dB
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone 63
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone		 68
SFDR Spurious-free dynamic range Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone		 70 dB
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone 73
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone		 75
Conversion time Serial conversion, time-to-output, 24 MHz clock 50 clock-cycles
Current consumption Internal 4.3 V equivalent reference(2) 0.42 mA
Current consumption VDDS as reference 0.6 mA
Reference voltage Equivalent fixed internal reference (input voltage scaling enabled). For best accuracy, the ADC conversion should be initiated through the TI-RTOS API in order to include the gain/offset compensation factors stored in FCFG1 4.3(2)(3) V
Reference voltage Fixed internal reference (input voltage scaling disabled). For best accuracy, the ADC conversion should be initiated through the TI-RTOS API in order to include the gain/offset compensation factors stored in FCFG1. This value is derived from the scaled value (4.3 V) as follows:
Vref = 4.3 V × 1408 / 4095		 1.48 V
Reference voltage VDDS as reference, input voltage scaling enabled VDDS V
Reference voltage VDDS as reference, input voltage scaling disabled VDDS / 2.82(3) V
Input impedance 200 kSamples/s, voltage scaling enabled. Capacitive input, Input impedance depends on sampling frequency and sampling time >1 MΩ
(1) Using IEEE Std 1241-2010 for terminology and test methods
(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V
(3) Applied voltage must be within Absolute Maximum Ratings (see Section 8.1 ) at all times
(4) No missing codes
(5) ADC_output = ∑(4n samples)  >> n,n = desired extra bits