SLASF44 may 2023 AFE78201 , AFE88201
PRODUCTION DATA
The AFEx8201 communicate with the system controller through a serial interface that supports either a UART-compatible two-wire bus or an SPI-compatible bus. Based on the hardware configuration, either interface can be enabled. Figure 7-17 and Figure 7-18 show the configurations to enable SPI mode and UART break mode (UBM), respectively. The SPI supports an 8-bit frame-by-frame CRC that is enabled by default, but can be disabled by the user. UBM does not support CRC, but does support the UART protocol parity bit.