ZHCSRW7 march   2023 AFE781H1 , AFE881H1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Timing Diagrams
    8. 6.8  Typical Characteristics: VOUT DAC
    9. 6.9  Typical Characteristics: ADC
    10. 6.10 Typical Characteristics: Reference
    11. 6.11 Typical Characteristics: HART Modem
    12. 6.12 Typical Characteristics: Power Supply
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Overview
        1. 7.3.1.1 DAC Resistor String
        2. 7.3.1.2 DAC Buffer Amplifier
        3. 7.3.1.3 DAC Transfer Function
        4. 7.3.1.4 DAC Gain and Offset Calibration
        5. 7.3.1.5 Programmable Slew Rate
        6. 7.3.1.6 DAC Register Structure and CLEAR State
      2. 7.3.2 Analog-to-Digital Converter (ADC) Overview
        1. 7.3.2.1 ADC Operation
        2. 7.3.2.2 ADC Custom Channel Sequencer
        3. 7.3.2.3 ADC Synchronization
        4. 7.3.2.4 ADC Offset Calibration
        5. 7.3.2.5 External Monitoring Inputs
        6. 7.3.2.6 Temperature Sensor
        7. 7.3.2.7 Self-Diagnostic Multiplexer
        8. 7.3.2.8 ADC Bypass
      3. 7.3.3 Programmable Out-of-Range Alarms
        1. 7.3.3.1 Alarm-Based Interrupts
        2. 7.3.3.2 Alarm Action Configuration Register
        3. 7.3.3.3 Alarm Voltage Generator
        4. 7.3.3.4 Temperature Sensor Alarm Function
        5. 7.3.3.5 Internal Reference Alarm Function
        6. 7.3.3.6 ADC Alarm Function
        7. 7.3.3.7 Fault Detection
      4. 7.3.4 IRQ
      5. 7.3.5 HART Interface
        1. 7.3.5.1  FIFO Buffers
          1. 7.3.5.1.1 FIFO Buffer Access
          2. 7.3.5.1.2 FIFO Buffer Flags
        2. 7.3.5.2  HART Modulator
        3. 7.3.5.3  HART Demodulator
        4. 7.3.5.4  HART Modem Modes
          1. 7.3.5.4.1 Half-Duplex Mode
          2. 7.3.5.4.2 Full-Duplex Mode
        5. 7.3.5.5  HART Modulation and Demodulation Arbitration
          1. 7.3.5.5.1 HART Receive Mode
          2. 7.3.5.5.2 HART Transmit Mode
        6. 7.3.5.6  HART Modulator Timing and Preamble Requirements
        7. 7.3.5.7  HART Demodulator Timing and Preamble Requirements
        8. 7.3.5.8  IRQ Configuration for HART Communication
        9. 7.3.5.9  HART Communication Using the SPI
        10. 7.3.5.10 HART Communication Using UART
        11. 7.3.5.11 Memory Built-In Self-Test (MBIST)
      6. 7.3.6 Internal Reference
      7. 7.3.7 Integrated Precision Oscillator
      8. 7.3.8 One-Time Programmable (OTP) Memory
    4. 7.4 Device Functional Modes
      1. 7.4.1 DAC Power-Down Mode
      2. 7.4.2 Reset
    5. 7.5 Programming
      1. 7.5.1 Communication Setup
        1. 7.5.1.1 SPI Mode
        2. 7.5.1.2 UART Mode
        3. 7.5.1.3 SPI Plus UART Mode
        4. 7.5.1.4 HART Functionality Setup Options
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 SPI Frame Definition
        2. 7.5.2.2 SPI Read and Write
        3. 7.5.2.3 Frame Error Checking
        4. 7.5.2.4 Synchronization
      3. 7.5.3 UART Interface
        1. 7.5.3.1 UART Break Mode (UBM)
          1. 7.5.3.1.1 Interface With FIFO Buffers and Register Map
      4. 7.5.4 Status Bits
      5. 7.5.5 Watchdog Timer
    6. 7.6 Register Maps
      1. 7.6.1 AFEx81H1 Registers
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 4-mA to 20-mA Current Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Start-Up Circuit
          2. 8.2.1.2.2 Current Loop Control
          3. 8.2.1.2.3 Input Protection and Rectification
          4. 8.2.1.2.4 System Current Budget
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

Typical Characteristics: VOUT DAC

at TA = 25°C, PVDD = VDD = IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted)

GUID-20220618-SS0I-BXKD-LCSD-F8QK5KMVQBVW-low.png
 
Figure 6-3 DAC DNL vs Digital Input Code
GUID-20220618-SS0I-JXDT-TK5B-PG5QT9QGLHVT-low.png
 
Figure 6-5 DAC INL vs Digital Input Code
GUID-20220618-SS0I-7MT5-PVVT-DL0JRWW8FSV7-low.png
 
Figure 6-7 MIN and MAX DAC DNL Range vs Temperature
GUID-20220618-SS0I-HXHC-WXCM-575DD1JLCWF8-low.png
 
Figure 6-9 DAC TUE vs Digital Input Code
GUID-20220618-SS0I-BF62-NWSR-2M65Z8TSC4LC-low.png
 
Figure 6-11 MIN and MAX DAC TUE vs Temperature
GUID-20220618-SS0I-FJZF-RRQN-DLVPTFVDXRZM-low.png
RANGE = 0
Figure 6-13 DAC Source and Sink Current Capability
GUID-20220618-SS0I-STVB-QS2V-2DTZ8CGPXDCD-low.pngFigure 6-15 DAC Gain Error vs Temperature
GUID-20220618-SS0I-J5FX-DMPP-Z9RMQB4CTSVJ-low.pngFigure 6-17 DAC Full Scale Error vs Temperature
GUID-20220618-SS0I-QRXB-KVPC-WGDHLFGJRQBW-low.png
DAC at midcode
Figure 6-19 DAC Output Noise, 0.1 Hz to 10 Hz
GUID-20220618-SS0I-4ZLS-QFD5-HVVX2NGXDWLS-low.png
 
Figure 6-21 DAC Settling Time vs Load (Rising Voltage Step)
GUID-20220618-SS0I-7B7Z-KBHJ-G57P2WPGVLRL-low.png
 
Figure 6-23 DAC Settling Time With Linear Slew Rate Control
GUID-20220618-SS0I-WCLG-XGGF-MZHM7QDP1TCD-low.png
 
Figure 6-25 DAC Glitch Impulse Rising Edge
GUID-20220618-SS0I-NGFG-FG7L-0DFJLTV2LLHD-low.pngFigure 6-27 DAC Supply Power On, PVDD = 1.8 V
GUID-20220618-SS0I-KBP5-CKCK-XCL1L348FDDL-low.png
1: 0.4-V to 2-V range, midcode 3: 0.3-V to 2.2-V range,
2: 0.2-V to 1-V range, midcode zero code
Figure 6-29 DAC PVDD Supply Collapse Response, RANGE = 1
GUID-20220618-SS0I-WBKC-2PBZ-NZHQM188N4QH-low.png
0.15-V to 1.25-V range, midcode
Figure 6-31 DAC VDD Supply Collapse Response,
RANGE = 0
GUID-20220927-SS0I-R0XJ-3SC6-JFRMBXJDMJCG-low.png
Ideal reference
Figure 6-33 DAC Output Voltage Long-Term Stability
GUID-20220618-SS0I-MM2N-7BQC-5ZSFPDPS4KXQ-low.png
 
Figure 6-4 DAC DNL vs Digital Input Code
GUID-20220618-SS0I-HL24-WT8P-H33VTSX6QFL1-low.png
 
Figure 6-6 DAC INL vs Digital Input Code
GUID-20220618-SS0I-NDHN-ZQHK-PV6MC9KSVN9L-low.png
 
Figure 6-8 MIN and MAX DAC INL Range vs Temperature
GUID-20220618-SS0I-KNW6-BQTC-BBFFKHJNF9DK-low.png
 
Figure 6-10 DAC TUE vs Digital Input Code
GUID-20220618-SS0I-R8NB-T7K4-5VR1JKFMFPV0-low.png
 
Figure 6-12 DAC RESET Response
GUID-20220618-SS0I-GJTR-X9QS-GRGKRLBD9LLT-low.png
RANGE = 1
Figure 6-14 DAC Source and Sink Current Capability
GUID-20220618-SS0I-QMC8-XVH7-HVZVV4Q7GKV8-low.pngFigure 6-16 DAC Offset Error vs Temperature
GUID-20220618-SS0I-SZ8Z-BS3S-FTKKXRR5RS0Z-low.pngFigure 6-18 DAC Zero Scale Error vs Temperature
GUID-20220618-SS0I-QGNK-JRWL-S1R04DHZLQ7Q-low.png
DAC at midcode
Figure 6-20 DAC Output Noise Density vs Frequency
GUID-20220618-SS0I-L2MR-XRGN-CKXR7MQL608G-low.png
 
Figure 6-22 DAC Settling Time vs Load (Falling Voltage Step)
GUID-20220618-SS0I-XJK0-J664-BJRT24X036LV-low.png
 
Figure 6-24 DAC Settling Time With Sinusoidal Slew Rate Control
GUID-20220618-SS0I-SD2F-3TT0-CJVXCTHQG20G-low.png
 
Figure 6-26 DAC Glitch Impulse Falling Edge
GUID-20220618-SS0I-KDT8-XSBC-CD486K0X107Q-low.pngFigure 6-28 DAC Supply Power On, PVDD = 3.3 V
GUID-20220618-SS0I-JSG2-FG2H-F3NC0J71NK9S-low.png
0.15-V to 1.25-V range, midcode
 
Figure 6-30 DAC PVDD Supply Collapse Response, RANGE = 0
GUID-20220618-SS0I-LD9L-96G9-G8Q0SDD1GP7V-low.png
0.4-V to 2-V range, midcode
Figure 6-32 DAC IOVDD Supply Collapse Response, RANGE = 1
GUID-20220618-SS0I-0VGQ-CGRV-RWSSBW0RPFNT-low.png
Internal Reference
Figure 6-34 DAC AC PSRR vs Frequency