ZHCSE95A October   2015  – October 2015 ADS9110

PRODUCTION DATA.  

1. 1 特性
2. 2 应用
3. 3 说明
4. 4 修订历史记录
5. 5 Pin Configuration and Functions
6. 6 Specifications
   1. 6.1  Absolute Maximum Ratings
   2. 6.2  ESD Ratings
   3. 6.3  Recommended Operating Conditions
   4. 6.4  Thermal Information
   5. 6.5  Electrical Characteristics
   6. 6.6  Timing Requirements: Conversion Cycle
   7. 6.7  Timing Requirements: Asynchronous Reset, NAP, and PD
   8. 6.8  Timing Requirements: SPI-Compatible Serial Interface
   9. 6.9  Timing Requirements: Source-Synchronous Serial Interface (External Clock)
   10. 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
   11. 6.11 Typical Characteristics
7. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
      1. 7.3.1 Converter Module
         1. 7.3.1.1 Sample-and-Hold Circuit
         2. 7.3.1.2 External Reference Source
         3. 7.3.1.3 Internal Oscillator
         4. 7.3.1.4 ADC Transfer Function
      2. 7.3.2 Interface Module
   4. 7.4 Device Functional Modes
      1. 7.4.1 RST State
      2. 7.4.2 ACQ State
      3. 7.4.3 CNV State
   5. 7.5 Programming
      1. 7.5.1 Data Transfer Frame
      2. 7.5.2 Interleaving Conversion Cycles and Data Transfer Frames
      3. 7.5.3 Data Transfer Protocols
         1. 7.5.3.1 Protocols for Configuring the Device
         2. 7.5.3.2 Protocols for Reading From the Device
            1. 7.5.3.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols
            2. 7.5.3.2.2 SPI-Compatible Protocols with Bus Width Options
            3. 7.5.3.2.3 Source-Synchronous (SRC) Protocols
               1. 7.5.3.2.3.1 Output Clock Source Options with SRC Protocols
               2. 7.5.3.2.3.2 Bus Width Options with SRC Protocols
               3. 7.5.3.2.3.3 Output Data Rate Options with SRC Protocols
      4. 7.5.4 Device Setup
         1. 7.5.4.1 Single Device: All multiSPI Options
         2. 7.5.4.2 Single Device: Minimum Pins for a Standard SPI Interface
         3. 7.5.4.3 Multiple Devices: Daisy-Chain Topology
         4. 7.5.4.4 Multiple Devices: Star Topology
   6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
         1. 7.6.1.1 PD_CNTL Register (address = 010h)
         2. 7.6.1.2 SDI_CNTL Register (address = 014h)
         3. 7.6.1.3 SDO_CNTL Register (address = 018h)
         4. 7.6.1.4 DATA_CNTL Register (address = 01Ch)
8. 8 Application and Implementation
   1. 8.1 Application Information
      1. 8.1.1 ADC Input Driver
      2. 8.1.2 Input Amplifier Selection
      3. 8.1.3 Antialiasing Filter
      4. 8.1.4 ADC Reference Driver
   2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
9. 9 Power-Supply Recommendations
   1. 9.1 Power-Supply Decoupling
   2. 9.2 Power Saving
      1. 9.2.1 NAP Mode
      2. 9.2.2 PD Mode
10. 10Layout
    1. 10.1 Layout Guidelines
       1. 10.1.1 Signal Path
       2. 10.1.2 Grounding and PCB Stack-Up
       3. 10.1.3 Decoupling of Power Supplies
       4. 10.1.4 Reference Decoupling
       5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
11. 11器件和文档支持
    1. 11.1 文档支持
       1. 11.1.1 相关文档　
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
12. 12机械封装和可订购信息