ZHCSBH3C May   2013  – March 2019 ADS8866

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      ADC 电源无需独立的 LDO
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: 3-Wire Operation
    7. 7.7 Timing Requirements: 4-Wire Operation
    8. 7.8 Timing Requirements: Daisy-Chain
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Equivalent Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Input
      2. 9.3.2 Reference
      3. 9.3.3 Clock
      4. 9.3.4 ADC Transfer Function
    4. 9.4 Device Functional Modes
      1. 9.4.1 CS Mode
        1. 9.4.1.1 3-Wire CS Mode
        2. 9.4.1.2 4-Wire CS Mode
      2. 9.4.2 Daisy-Chain Mode
        1. 9.4.2.1 Daisy-Chain Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 ADC Reference Driver
      2. 10.1.2 ADC Input Driver
        1. 10.1.2.1 Input Amplifier Selection
        2. 10.1.2.2 Charge-Kickback Filter
    2. 10.2 Typical Applications
      1. 10.2.1 DAQ Circuit for a 10-µs, Full-Scale Step Response
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
      2. 10.2.2 DAQ Circuit for Lowest Distortion and Noise Performance at 100 kSPS
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
      3. 10.2.3 Ultralow-Power DAQ Circuit at 10 kSPS
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Power Saving
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 接收文档更新通知
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 术语表
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10.2.3.2 Detailed Design Procedure

The data acquisition circuit shown in Figure 54 is optimized for using the ADS8866 at a reduced throughput of 10 kSPS

In order to save power, this circuit is operated on a single 3.3-V supply. The circuit uses the OPA333 with a maximum quiescent current of 28 µA in order to drive the ADC input. The input amplifier is configured in a modified unity-gain buffer configuration. The filter capacitor at the ADC inputs attenuates the sampling charge injection noise from the ADC but effects the stability of the input amplifiers by degrading the phase margin. This attenuation requires a series isolation resistor to maintain amplifier stability. The value of the series resistor is directly proportional to the open-loop output impedance of the driving amplifier to maintain stability, which is high (in the order of kΩ) in the case of low-power amplifiers such as the OPA333. Therefore, a high value of 1 kΩ is selected for the series resistor at the ADC inputs. However, this series resistor creates an additional voltage drop in the signal path, thereby leading to linearity and distortion issues. The dual-feedback configuration used in Figure 54 corrects for this additional voltage drop and maintains system performance at ultralow-power consumption.