ZHCSBH3C May   2013  – March 2019 ADS8866

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      ADC 电源无需独立的 LDO
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: 3-Wire Operation
    7. 7.7 Timing Requirements: 4-Wire Operation
    8. 7.8 Timing Requirements: Daisy-Chain
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Equivalent Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Input
      2. 9.3.2 Reference
      3. 9.3.3 Clock
      4. 9.3.4 ADC Transfer Function
    4. 9.4 Device Functional Modes
      1. 9.4.1 CS Mode
        1. 9.4.1.1 3-Wire CS Mode
        2. 9.4.1.2 4-Wire CS Mode
      2. 9.4.2 Daisy-Chain Mode
        1. 9.4.2.1 Daisy-Chain Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 ADC Reference Driver
      2. 10.1.2 ADC Input Driver
        1. 10.1.2.1 Input Amplifier Selection
        2. 10.1.2.2 Charge-Kickback Filter
    2. 10.2 Typical Applications
      1. 10.2.1 DAQ Circuit for a 10-µs, Full-Scale Step Response
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
      2. 10.2.2 DAQ Circuit for Lowest Distortion and Noise Performance at 100 kSPS
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
      3. 10.2.3 Ultralow-Power DAQ Circuit at 10 kSPS
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Power Saving
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 接收文档更新通知
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 术语表
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.4.1.1 3-Wire CS Mode

This interface option is most useful when a single ADC is connected to an SPI-compatible digital host. In this interface option, DIN can be connected to DVDD and CONVST functions as CS (as shown in Figure 43). As shown in Figure 44, a CONVST rising edge forces DOUT to 3-state, samples the input signal, and causes the device to enter a conversion phase. Conversion is done with the internal clock and continues regardless of the state of CONVST. As a result, CONVST (functioning as CS) can be pulled low after the start of the conversion to select other devices on the board. However, CONVST must return high before the minimum conversion time (tconv-min) elapses and is held high until the maximum possible conversion time (tconv-max) elapses.

ADS8866 ai_cs_3wire_conex_bas557.gifFigure 43. Connection Diagram: 3-Wire CS Mode (DIN = 1)
ADS8866 ai_cs_3wire_tim_bas557.gifFigure 44. Interface Timing Diagram: 3-Wire CS Mode (DIN = 1)

When conversion is complete, the device enters an acquisition phase and powers down. CONVST (functioning as CS) can be brought low after the maximum conversion time (tconv-max) elapses. On the CONVST falling edge, DOUT comes out of 3-state and the device outputs the MSB of the data. The lower data bits are output on subsequent SCLK falling edges. Data can be read at either SCLK falling or rising edges. Note that with any SCLK frequency, reading data at SCLK falling edge requires the digital host to clock in the data during the th_CK_DO-min time frame. DOUT goes to 3-state after the 16th SCLK falling edge or when CONVST goes high, whichever occurs first.