SLAS669E September 2010 – may 2020 ADS5400-SP
PRODUCTION DATA.
Each register function is explained in detail below.
Address (hex) | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
---|---|---|---|---|---|---|---|---|
0x00 | Analog Gain Adjustment bits<11:4> | |||||||
Defaults | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
BIT <7:0> | Analog gain adjustment (most significant 8 bits of a 12 bit word) | ||
All 12-bits in this adjustment in address 0x00 and 0x01 set to 0000 0000 0000 = fullscale analog input 2.0VPP | |||
All 12-bits in this adjustment in address 0x00 and 0x01 set to 1111 1111 1111 = fullscale analog input 1.52VPP | |||
Step adjustment resolution is 120µV. | |||
Can be used for one-time setting or continual calibration of analog signal path gain. |
Address (hex) | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
---|---|---|---|---|---|---|---|---|
0x01 | Analog Gain Adjustment bits<3:0> | 3 or 4-pin SPI | SPI Reset | 0 | 0 | |||
Defaults | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Address (hex) | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
---|---|---|---|---|---|---|---|---|
0x02 | Coarse Clock Phase Adjustment bits<4:0> | 0 | Clock Divider | Single or Dual Bus | ||||
Defaults | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Address (hex) | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
---|---|---|---|---|---|---|---|---|
0x03 | Fine Clock Phase Adjustment bits<5:0> | 0 | Analog Offset bit<8> | |||||
Defaults | 0 | 0 | 0 | 0 | 0 | 0 | 0 | factory set |
Address (hex) | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
---|---|---|---|---|---|---|---|---|
0x04 | Analog Offset Control bits<7:0> | |||||||
Defaults | factory set |
Address (hex) | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
---|---|---|---|---|---|---|---|---|
0x05 | Temp Sensor | Powerdown | reserved | Sync Mode | Data Format | Reference | Stagger Output | 0 |
Defaults | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
BIT <0> | RESERVED | ||
0 | set to 0 if writing this register | ||
1 | do not set to 1 | ||
BIT <1> | Stagger Output Bus | ||
0 | Output bus A and B aligned | ||
1 | Output bus A and B staggered (see timing diagrams) | ||
BIT <2> | Enable External Reference | ||
0 | Enable internal reference | ||
1 | Enable external reference | ||
BIT <3> | Set Data Output Format | ||
0 | Enable offset binary | ||
1 | Enable two's complement | ||
BIT <4> | Set Sync Mode | ||
0 | Disable data synchronization mode | ||
1 | Enable data synchronization mode | ||
When enabled, the OVR pin(s) are replaced with SYNC output signal(s). The SYNC output signal is time-aligned with the output data matching the corresponding input sample and RESET input pulse | |||
BIT <5> | RESERVED | ||
0 | |||
1 | set to 1 if writing this register | ||
BIT <6> | Powerdown | ||
0 | device active | ||
1 | device in low power mode (sleep mode) | ||
BIT <7> | Temperature Sensor | ||
0 | temperature sensor inactive | ||
1 | temperature sensor active, independent of powerdown bit in Bit<6>, allows reading of temp sensor while the rest of the ADC is in sleep mode |
Address (hex) | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
---|---|---|---|---|---|---|---|---|
0x06 | Data output mode | LVDS termination | LVDS current | Force LVDS outputs | ||||
Defaults | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
Address (hex) | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
---|---|---|---|---|---|---|---|---|
0x08 | Die temperature bits<7:0> | |||||||
Defaults | depends on reading from temperature sensor |
BIT <7:0> | Die temperature readout | ||
if enabled in register 0x05. To obtain the die temperature in Celsius, convert the 8-bit word to decimal and subtract 78. | |||
<7:0> = 0x00 = 00000000, measured temperature is 0-78 = -78°C | |||
<7:0> = 0x73 = 01110011, measured temperature is 115 - 78 = 37°C | |||
<7:0> = 0xAF, measured temperature is 175 - 78 = 97°C |
Address (hex) | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
---|---|---|---|---|---|---|---|---|
0x09 | 000 0000 | Memory error | ||||||
Defaults | 000 0000 | 0 |
BIT <7:1> | RESERVED | ||
set to 0 if writing this register | |||
do not set to 1 | |||
BIT <0> | Memory Error Indicator | ||
Registers 0x00 through 0x07 have multiple redundancy. If any copy disagrees with the others, an error is flagged in this bit. This is for systems that require the highest level of assurance that the device remains programmed in the proper state and indication of an error if something changes unexpectedly. |
Address (hex) | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
---|---|---|---|---|---|---|---|---|
0x0A | 0000 0000 | |||||||
Defaults | 0000 0000 |
BIT <7:0> | RESERVED | ||
set to 0 if writing this register | |||
do not set to 1 |
Address (hex) | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
---|---|---|---|---|---|---|---|---|
0x17 - 0x1E | Die ID | |||||||
Defaults | factory set |
BIT <7:0> | Die Identification Bits | ||
Each of these eight registers contains 8-bits of a 64-bit unique die identifier. | |||
Address (hex) | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
---|---|---|---|---|---|---|---|---|
0x1F | Die Revision Number | |||||||
Defaults | factory set |
BIT <7:0> | Die revision | ||
Provides design revision information. | |||