ZHCSMK4A september   2022  – july 2023 ADS131B26-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 说明（续）
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagram
    9. 7.9 Typical Characteristics
  9. 8 Parameter Measurement Information
    1. 8.1 Offset Drift Measurement
    2. 8.2 Gain Drift Measurement
    3. 8.3 Noise Performance
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Naming Conventions
      2. 9.3.2 Precision Voltage References (REFA, REFB)
      3. 9.3.3 Clocking (MCLK, OSCM, OSCD)
      4. 9.3.4 ADC1y
        1. 9.3.4.1 ADC1y Input Multiplexer
        2. 9.3.4.2 ADC1y Programmable Gain Amplifier (PGA)
        3. 9.3.4.3 ADC1y ΔΣ Modulator
        4. 9.3.4.4 ADC1y Digital Filter
        5. 9.3.4.5 ADC1y Offset and Gain Calibration
        6. 9.3.4.6 ADC1y Conversion Data
      5. 9.3.5 ADC2y
        1. 9.3.5.1 ADC2y Input Multiplexer
        2. 9.3.5.2 ADC2y Programmable Gain Amplifier (PGA)
        3. 9.3.5.3 ADC2y ΔΣ Modulator
        4. 9.3.5.4 ADC2y Digital Filter
        5. 9.3.5.5 ADC2y Offset and Gain Calibration
        6. 9.3.5.6 ADC2y Sequencer
        7. 9.3.5.7 VCMy Buffers
        8. 9.3.5.8 ADC2y Measurement Configurations
        9. 9.3.5.9 ADC2y Conversion Data
      6. 9.3.6 ADC3y
      7. 9.3.7 General-Purpose Digital Inputs and Outputs (GPIO0 to GPIO4)
        1. 9.3.7.1 GPIOx PWM Output Configuration
        2. 9.3.7.2 GPIOx PWM Input Readback
      8. 9.3.8 General-Purpose Digital Inputs and Outputs (GPIO0A, GPIO1A, GPIO0B, GPIO1B)
      9. 9.3.9 Monitors and Diagnostics
        1. 9.3.9.1  Supply Monitors
        2. 9.3.9.2  Clock Monitors
        3. 9.3.9.3  Digital Monitors
          1. 9.3.9.3.1 Register Map CRC
          2. 9.3.9.3.2 Memory Map CRC
          3. 9.3.9.3.3 GPIO Readback
        4. 9.3.9.4  Communication Monitors
        5. 9.3.9.5  Fault Flags and Fault Masking
        6. 9.3.9.6  FAULT Pin
        7. 9.3.9.7  Diagnostics and Diagnostic Procedure
        8. 9.3.9.8  Indicators
        9. 9.3.9.9  Conversion and Sequence Counters
        10. 9.3.9.10 Supply Voltage Readback
        11. 9.3.9.11 Temperature Sensors (TSA, TSB)
        12. 9.3.9.12 Test DACs (TDACA, TDACB)
        13. 9.3.9.13 Open-Wire Detection
        14. 9.3.9.14 Missing Host Detection and MHD Pin
        15. 9.3.9.15 Overcurrent Comparators (OCCA, OCCB)
          1. 9.3.9.15.1 OCCA and OCCB Pins
          2. 9.3.9.15.2 Overcurrent Indication Response Time
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Up and Reset
        1. 9.4.1.1 Power-On Reset (POR)
        2. 9.4.1.2 RESETn Pin
        3. 9.4.1.3 RESET Command
      2. 9.4.2 Operating Modes
        1. 9.4.2.1 Active Mode
        2. 9.4.2.2 Standby Mode
        3. 9.4.2.3 Power-Down Mode
      3. 9.4.3 ADC Conversion Modes
        1. 9.4.3.1 ADC1y and ADC3y Conversion Modes
          1. 9.4.3.1.1 Continuous-Conversion Mode
          2. 9.4.3.1.2 Single-Shot Conversion Mode
          3. 9.4.3.1.3 Global-Chop Mode
            1. 9.4.3.1.3.1 Overcurrent Indication Response Time in Global-Chop Mode
        2. 9.4.3.2 ADC2y Sequencer Operation and Sequence Modes
          1. 9.4.3.2.1 Continuous Sequence Mode
          2. 9.4.3.2.2 Single-Shot Sequence Mode
          3. 9.4.3.2.3 Synchronized Single-Shot Sequence Mode Based on ADC1y Conversion Starts
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Serial Interface Signals
          1. 9.5.1.1.1 Chip Select (CSn)
          2. 9.5.1.1.2 Serial Data Clock (SCLK)
          3. 9.5.1.1.3 Serial Data Input (SDI)
          4. 9.5.1.1.4 Serial Data Output (SDO)
          5. 9.5.1.1.5 Data Ready (DRDYn)
        2. 9.5.1.2 Serial Interface Communication Structure
          1. 9.5.1.2.1 SPI Communication Frames
          2. 9.5.1.2.2 SPI Communication Words
          3. 9.5.1.2.3 STATUS Word
          4. 9.5.1.2.4 Communication Cyclic Redundancy Check (CRC)
          5. 9.5.1.2.5 Commands
            1. 9.5.1.2.5.1 NULL (0000 0000 0000 0000b)
            2. 9.5.1.2.5.2 RESET (0000 0000 0001 0001b)
            3. 9.5.1.2.5.3 LOCK (0000 0101 0101 0101b)
            4. 9.5.1.2.5.4 UNLOCK (0000 0110 0101 0101b)
            5. 9.5.1.2.5.5 WREG (011a aaaa aaa0 0nnnb)
            6. 9.5.1.2.5.6 RREG (101a aaaa aaan nnnnb)
          6. 9.5.1.2.6 SCLK Counter
          7. 9.5.1.2.7 SPI Timeout
          8. 9.5.1.2.8 Reading ADC1A, ADC1B, ADC2A, ADC2B, ADC3A, and ADC3B Conversion Data
          9. 9.5.1.2.9 DRDYn Pin Behavior
    6. 9.6 Register Map
      1. 9.6.1 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Unused Inputs and Outputs
      2. 10.1.2 Minimum Interface Connections
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Current Shunt Measurement
        2. 10.2.2.2 Battery Pack Voltage Measurement
        3. 10.2.2.3 Other Voltage Measurements
        4. 10.2.2.4 Shunt Temperature Measurement
        5. 10.2.2.5 Analog Output Temperature Sensor Measurement
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Power-Supply Options
        1. 10.3.1.1 Single Unregulated External 4-V to 16-V Supply (3.3-V Digital I/O Levels)
        2. 10.3.1.2 Single Regulated External 3.3-V Supply (3.3-V Digital IO Levels)
        3. 10.3.1.3 Single Regulated External 5-V Supply (5-V Digital I/O Levels)
      2. 10.3.2 Power-Supply Sequencing
      3. 10.3.3 Power-Supply Decoupling
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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订购信息

7.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +105°C; typical specifications are at TA = 25°C; all specifications are at APWR = 5 V, DPWR = 5 V, IOVDD = 3.3 V, external clock, fCLK = 8.192 MHz, global-chop mode disabled, ADC1y and ADC3y data rate = 1 kSPS (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT MEASUREMENT ADCS (ADC1A, ADC1B)
Resolution 24 Bits
Gain settings 4, 8, 16, 32 V/V
fDATA Output data rate fCLK = 8.192 MHz 500 64k SPS
Absolute input current All data rates, all gains, global-chop enabled or disabled, VCPy = VCNy = 0 V ±0.5 nA
Differential input current All data rates, all gains, global-chop enabled or disabled, VCPy = VCNy = 0 V –5 ±1 5 nA
Differential input impedance All data rates, all gains, global-chop enabled or disabled 1.8 MΩ
Offset error (input referred) Gain = 4, global-chop disabled ±1 µV
Gain = 8 to 32, global-chop disabled ±15
All gains, global-chop enabled –1.5 ±0.5 1.5
Offset drift All gains, global-chop disabled 20 100 nV/°C
All gains, global-chop enabled 1 7
Gain error TA = 25°C, all gains, single-ended operation with CNy held at AGNDy, including initial accuracy of REFy –0.15% ±0.05% 0.15%
Gain drift All gains, single-ended operation with CNy held at AGNDy, including drift of REFy 5 20 ppm/°C
Gain long-term drift 1000 hours at 85°C,
all gains, including long-term drift of REFy		 ±100 ppm
Gain match Between gain settings –0.12% ±0.03% 0.12%
Noise (input referred) Gain = 8, fDATA = 1 kSPS 0.65 µVRMS
CMRR Common-mode rejection ratio At DC, global-chop disabled 110 dB
At DC, global-chop enabled 113
PSRR Power-supply rejection ratio APWR at DC, global-chop enabled or disabled 133 dB
DPWR at DC, global-chop enabled or disabled 133
AVDD at DC, global-chop enabled or disabled 115
IOVDD at DC, global-chop enabled or disabled 131
VOLTAGE AND TEMPERATURE MEASUREMENT ADCS (ADC2A, ADC2B)
Resolution 16 Bits
Gain settings 1, 2, 4 V/V
Absolute input current OSR2y = 64, all gains, VVxy = 0 V ±0.2 nA
Differential input current OSR2y = 64, all gains, VVxy = 0 V ±0.4 nA
Differential input impedance OSR2y = 64, all gains 15 MΩ
OSR2y = 128, all gains 30
OSR2y = 256, all gains 60
OSR2y = 512, all gains 120
Offset error (input referred) Gain = 1 –350 ±85 350 µV
Gain = 2 and 4 –25 ±5 25
Offset drift Gain = 1 60 300 nV/°C
Gain = 2 and 4 30 150
Gain error TA = 25°C, all gains,
including initial accuracy of REFy		 –0.3% ±0.1% 0.3%
Gain drift All gains, including drift of REFy 5 20 ppm/°C
Gain long-term drift 1000 hours at 85°C,
all gains, including long-term drift of REFy		 ±100 ppm
Gain match Between gain settings –0.15% ±0.06% 0.15%
CMRR Common-mode rejection ratio At DC 95 dB
PSRR Power-supply rejection ratio APWR at DC 103 dB
DPWR at DC 103
AVDD at DC 91
IOVDD at DC 96
BATTERY VOLTAGE MEASUREMENT ADCS (ADC3A, ADC3B)
Resolution 24 Bits
Gain settings 1, 2, 4 V/V
fDATA Output data rate fCLK = 8.192 MHz 500 64k SPS
Absolute input current fDATA = 1 kSPS, all gains, global-chop enabled or disabled, VVPy = VVNy = 0 V ±0.1 nA
Differential input current fDATA = 1 kSPS, all gains, global-chop enabled or disabled, VVPy = VVNy = 0 V –2 ±0.1 2 nA
Differential input impedance fDATA = 64 kSPS, all gains, global-chop enabled or disabled 15 MΩ
fDATA = 16 kSPS, all gains, global-chop enabled or disabled 60
fDATA = 4 kSPS, all gains, global-chop enabled or disabled 250
fDATA = 1 kSPS, all gains, global-chop enabled or disabled 1000
Offset error (input referred) All gains, global-chop disabled –400 ±80 400 µV
All gains, global-chop enabled –10 ±3 10
Offset drift All gains, global-chop disabled 50 300 nV/°C
All gains, global-chop enabled 4 15
Gain error TA = 25°C, all gains, single-ended operation with VNy held at AGNDy, including initial accuracy of REFy –0.3% ±0.1% 0.3%
Gain drift All gains, single-ended operation with VNy held at AGNDy, including drift of REFy 5 20 ppm/°C
Gain long-term drift 1000 hours at 85°C,
all gains, including long-term drift of REFy		 ±100 ppm
Gain match Between gain settings –0.18% ±0.06% 0.18%
Noise (input referred) Gain = 4, fDATA = 1 kSPS 3 µVRMS
CMRR Common-mode rejection ratio At DC, global-chop disabled 114 dB
At DC, global-chop enabled 120
PSRR Power-supply rejection ratio APWR at DC, global-chop enabled or disabled 123 dB
DPWR at DC, global-chop enabled or disabled 123
AVDD at DC, global-chop enabled or disabled 93
IOVDD at DC, global-chop enabled or disabled 113
PRECISION VOLTAGE REFERENCES (REFA, REFB)
VREFA,
VREFB		 Reference voltage 1.25 V
Accuracy TA = 25°C –0.15% ±0.05% 0.15%
Temperature drift 3 15 ppm/°C
Output current Source only,
available for external loads on RCAPy pin		 250 µA
Short-circuit current limit Sink or source –10 10 mA
Start-up time 1-μF capacitor on RCAPy, 0.01% settling 8 ms
MAIN OSCILLATOR (OSCM)
fOSCM Frequency 8.192 MHz
Accuracy –2.5% 2.5%
DIAGNOSTIC OSCILLATOR (OSCD)
fOSCD Frequency 8.192 MHz
Accuracy –2.5% 2.5%
OVERCURRENT COMPARATORS (OCCA, OCCB)
Offset error (input referred) All gains –500 ±20 500 µV
Gain error All gains, including error of REFy –0.5% ±0.2% 0.5%
TEMPERATURE SENSORS (TSA, TSB)
TSOffset Output voltage TA = 25°C 118.4 mV
TSTC Temperature coefficient 410 µV/°C
COMMON-MODE OUTPUT BUFFERS (VCMA, VCMB)
VCMA, VCMB Common-mode output voltage 0.75 0.78 0.81 V
Output current Sink or source –1 1 mA
Short-circuit current limit Sink or source –5 5 mA
Capacitive load 100 pF
TEST DACS (TDACA, TDACB)
Output voltage settings 1 × VREFy / 40
2 × VREFy / 40
4 × VREFy / 40
9 × VREFy / 40
18 × VREFy / 40
36 × VREFy / 40
–4 × VREFy / 40
–9 × VREFy / 40		 V
Accuracy ±0.3%
Drift Positive output voltages 6 35 ppm/°C
Negative output voltages 12 80
OPEN-WIRE DETECTION CURRENT SOURCES AND SINKS (OWD1A, OWD1B, OWD2A, OWD2B, OWD3A, OWD3B)
Current source settings 4, 40, 240  µA
Current sink settings 4, 40, 240  µA
Current source accuracy ±8%
Current sink accuracy ±8%
DIGITAL INPUTS/OUTPUTS (GPIO0A, GPIO1A, GPIO0B, GPIO1B)
VIL Logic input level, low AGNDy 0.3 AVDD V
VIH Logic input level, high 0.7 AVDD AVDD V
VOL Logic output level, low IOL = –100 µA 0.2 AVDD V
VOH Logic output level, high IOH = 100 µA 0.8 AVDD V
IIN Input current AGNDy < VDigital Input < AVDD –1 1 µA
Short-circuit current limit Sink or source –8 8 mA
DIGITAL INPUTS/OUTPUTS (CSn, SCLK, SDI, SDO, RESETn, DRDYn, CLK, GPIO0/MHD, GPIO1, GPIO2/FAULT, GPIO3/OCCA, GPIO4/OCCB)
VIL Logic input level, low DGND 0.3 IOVDD V
VIH Logic input level, high 0.7 IOVDD IOVDD V
VOL Logic output level, low IOL = –1 mA 0.2 IOVDD V
VOH Logic output level, high IOH = 1 mA 0.8 IOVDD V
IIN Input current DGND < VDigital Input < IOVDD –1 1 µA
Short-circuit current limit Sink or source –80 80 mA
CLOCK MONITORS
fMCLK_WD_TH Main clock (MCLK) watchdog frequency threshold Watchdog indicates a fault when MCLK frequency drops below frequency threshold 300 kHz
fOSCD_WD_TH Diagnostic oscillator (OSCD) watchdog frequency threshold Watchdog indicates a fault when OSCD frequency drops below frequency threshold 300 kHz
MCLK_FAULT_TH Main clock fault detection frequency threshold Difference in clock frequencies between MCLK and OSCD to generate a fault 10%
POWER SUPPLY MONITORS
AVDD_UV_TH AVDD undervoltage threshold 2.9 2.95 3.0 V
AVDD_OV_TH AVDD overvoltage threshold 3.8 3.9 4.0 V
IOVDD_UV_TH IOVDD undervoltage threshold IOVDD_UV_TH = 1b 2.9 2.95 3.0 V
IOVDD_UV_TH = 0b 4.2 4.3 4.4
IOVDD_OV_TH IOVDD overvoltage threshold IOVDD_OV_TH = 1b 3.8 3.9 4.0 V
IOVDD_OV_TH = 0b 5.6 5.75 5.9
DVDD_UV_TH DVDD undervoltage threshold 1.55 1.6 1.65 V
DVDD_OV_TH DVDD overvoltage threshold 1.90 1.95 2.0 V
AVDD_OSC_MAG AVDD oscillation detection magnitude Amplitude required to generate fault 500 mVpp
AVDD_OSC_FREQ AVDD oscillation detection input frequency Oscillation frequency range to generate fault 2 500 kHz
IOVDD_OSC_MAG IOVDD oscillation detection magnitude Amplitude required to generate fault 500 mVpp
IOVDD_OSC_FREQ IOVDD oscillation detection input frequency Oscillation frequency range to generate fault 2 500 kHz
DVDD_OSC_MAG DVDD oscillation detection magnitude Amplitude required to generate fault 500 mVpp
DVDD_OSC_FREQ DVDD oscillation detection input frequency Oscillation frequency range to generate fault 2 500 kHz
AVDD_OTW_TH AVDD overtemperature warning thresholds –60
100
120
140		 °C
AVDD overtemperature warning threshold accuracy ±2 °C
IOVDD_OTW_TH IOVDD overtemperature warning thresholds –60
100
120
140		 °C
IOVDD overtemperature warning threshold accuracy ±2 °C
ADC2y power-supply readback attenuation factor APWR 103
DPWR 103
AVDD 4
IOVDD 4
DVDD 2
ADC2y power-supply readback accuracy OSR2y = 128, MUX2y_DELAY ≥ 256 × tMCLK ±1%
AVDD_POR_TH AVDD POR release threshold 2.6 2.7 2.85 V
IOVDD_POR_TH IOVDD POR release threshold 2.6 2.7 2.85 V
DVDD_POR_TH DVDD POR release threshold 1.4 1.5 1.6 V
FAULT MONITOR RESPONSE TIMES
tp(AVDD_OV) AVDD overvoltage detection response time Delay time from AVDD exceeding AVDD overvoltage threshold to FAULT pin active 4 µs
tp(IOVDD_OV) IOVDD overvoltage detection response time Delay time from IOVDD exceeding IOVDD overvoltage threshold to FAULT pin active 4 µs
tp(DVDD_OV) DVDD overvoltage detection response time Delay time from DVDD exceeding DVDD overvoltage threshold to FAULT pin active 4 µs
tp(AVDD_UV) AVDD undervoltage detection response time Delay time from AVDD dropping below AVDD undervoltage threshold to FAULT pin active 4 µs
tp(IOVDD_UV) IOVDD undervoltage detection response time Delay time from IOVDD dropping below IOVDD undervoltage threshold to FAULT pin active 4 µs
tp(DVDD_UV) DVDD undervoltage detection response time Delay time from DVDD dropping below DVDD undervoltage threshold to FAULT pin active 4 µs
tp(AVDD_OSC) AVDD oscillation detection response time Delay time from AVDD oscillations exceeding AVDD oscillation threshold to FAULT pin active 30 µs
tp(IOVDD_OSC) IOVDD oscillation detection response time Delay time from IOVDD oscillations exceeding IOVDD oscillation threshold to FAULT pin active 30 µs
tp(DVDD_OSC) DVDD oscillation detection response time Delay time from DVDD oscillations exceeding DVDD oscillation threshold to FAULT pin active 30 µs
tp(AVDD_CL) AVDD current limit detection response time Delay time from AVDD exceeding AVDD current limit threshold to FAULT pin active 40 µs
tp(IOVDD_CL) IOVDD current limit detection response time Delay time from IOVDD exceeding IOVDD current limit threshold to FAULT pin active 40 µs
tp(AVDD_OTW) AVDD overtemperature warning response time Delay time from AVDD exceeding AVDD overtemperature warning threshold to FAULT pin active 300 µs
tp(IOVDD_OTW) IOVDD overtemperature warning response time Delay time from IOVDD exceeding IOVDD overtemperature warning threshold to FAULT pin active 300 µs
tp(AVDD_POR) AVDD POR detection response time Delay time from AVDD dropping below AVDD POR threshold to FAULT pin active 30 µs
tp(IOVDD_POR) IOVDD POR detection response time Delay time from IOVDD dropping below IOVDD POR threshold to FAULT pin active 30 µs
tp(DVDD_POR) DVDD POR detection response time Delay time from DVDD dropping below DVDD POR threshold to FAULT pin active 30 µs
tp(DGND_OPEN) DGND open detection response time Delay time from DGND pin disconnected to FAULT pin active 4 µs
tp(AGNDy_OPEN) AGNDy open detection response time Delay time from AGNDy pin disconnected to FAULT pin active 4 µs
tp(MEM_MAP_CRC) Memory map CRC fault detection response time Delay time from bit flip occurence in memory map to FAULT pin active 69 138 tOSCD
tp(REG_MAP_CRC) Register map CRC fault detection response time Delay time from bit flip occurence in register map to FAULT pin active 1024 2048 tOSCD
tp(MCLK_WD) Main clock watchdog response time Delay time from main clock watchdog timeout to FAULT pin active 2 µs
tp(OSCD_WD) Diagnostic oscillator watchdog response time Delay time from diagnostic oscillator watchdog timeout to FAULT pin active 2 µs
tp(MCLK_FAULT) Main clock fault detection response time Delay time from main clock fault detection to FAULT pin active 4096 tMCLK
AVDD LDO
AVDD Output voltage 3.1 3.3 3.5 V
Load current Available to external circuitry on the AVDD pin 20 mA
Short-circuit current limit 60 mA
Load regulation 1 mV/mA
IOVDD LDO
IOVDD Output voltage 3.1 3.3 3.5 V
Load current Available to external circuitry on the IOVDD pin 20 mA
Short-circuit current limit 60 mA
Load regulation 1 mV/mA
SUPPLY CURRENTS
IAPWR APWR supply current Power-down mode 0.01 mA
Standby mode 0.46
Active mode, all ADCs disabled 0.8
Active mode, all ADCs enabled and converting
(all features enabled, no external load on AVDD LDO)		 6.3 7.7
APWR supply current per individual ADC ADC1y enabled and converting, all gains, all data rates 1.75
ADC2y enabled and converting, all gains, all data rates 0.5
ADC3y enabled and converting, all gains, all data rates 0.5
IDPWR DPWR supply current(1) Power-down mode 0.01 mA
Standby mode 0.4
Active mode, all ADCs disabled 0.8
Active mode, all ADCs enabled and converting
(all features enabled, no external load on IOVDD LDO)		 1.1 1.7
DPWR supply current per individual ADC(1) ADC1y enabled and converting, all data rates 0.06
ADC2y enabled and converting, all data rates 0.06
ADC3y enabled and converting, all data rates 0.06
IAVDD AVDD supply current APWR shorted to AVDD, i.e. AVDD LDO bypassed.
Active mode, all ADCs enabled and converting
(all features enabled)		 6.3 mA
IIOVDD IOVDD supply current(1) DPWR shorted to IOVDD, i.e. IOVDD LDO bypassed.
Active mode, all ADCs enabled and converting
(all features enabled)		 1.1 mA
PD Power dissipation Active mode, all ADCs enabled and converting
(all features enabled, no external load on IOVDD LDO)		 37 mW
(1) Currents measured with SPI idle.