ZHCSE48 数据表 | 德州仪器 TI.com.cn

ZHCSE48B September 2015 – January 2019 ADC31JB68

PRODUCTION DATA.

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RTA|40
- MPQF134A

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RTA|40
- QFND447B

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6.8 Timing Requirements

typical values at T_A = 25°C, full temperature range is T_MIN = –40°C to T_MAX = 85°C, ADC sampling rate = 500 MSPS, 50% clock duty cycle, VA3.0 = 3 V; VA1.8 = 1.8 V; VA1.2 = VACLK1.2 = 1.2 V; –1 dBFS differential input, and R_(term) = 100 Ω (unless otherwise noted) (see Figure 1 and Figure 2 for timing diagrams)

PARAMETER		NOTES	MIN	NOM	MAX	UNIT
ADC SAMPLING INSTANT TIMING CHARACTERISTICS
F_S	Sampling rate	Equal to F_CLKIN / CLKDIV	100		500	MSPS
F_CLKIN	Input clock frequency at CLKIN inputs	CLKDIV = 1	100		500	MHz
		CLKDIV = 2	200		1000
		CLKDIV = 4	400		2000
DC	Input clock (CLKIN) duty cycle	CLKDIV = 1		50% ± 20%
DC	Input clock (CLKIN) duty cycle	CLKDIV = 2 or CLKDIV = 4		50% ± 5%
t_LAT-ADC	ADC core latency	Delay from a reference sampling instant to the boundary of the internal LMFC where the reference sample is the first sample of the next transmitted multi-frame. In this device, the frame clock period is equal to the sampling clock period.		7		Frame clock cycles
t_J	Additive sampling aperture jitter	Depends on input CLKIN differential edge rate at the zero crossing, dV_SS/dt, tested with 5 V/ns edge rate.				fs
		CLKDIV = 1		80
		CLKDIV = 2, 4		90
OVER-RANGE INTERFACE TIMING CHARACTERISTICS (SDO/OVR⁽¹⁾)
t_ODH	OVR assertion delay	Functional delay between an overrange value sampled and OVR asserted		8		Frame clock cycles
t_ODL	OVR de-assertion delay	Functional delay between first underrange value sampled until OVR de-assertion, configurable via SPI				Frame clock cycles
		Configured for minimum delay		t_ODH
		Configured for maximum delay		t_ODH + 15
SYSREF TIMING CHARACTERISTICS
t_PH-SYS	SYSREF assertion duration	Required duration of SYSREF assertion after rising edge event	2			Frame clock cycles
t_PL-SYS	SYSREF de-assertion duration	Required duration of SYSREF de-assertion after falling edge event	2			Frame clock cycles
t_S-SYS	SYSREF setup time	Relative to CLKIN rising edge			350	ps
t_H-SYS	SYSREF hold time	Relative to CLKIN rising edge			0	ps
JESD204B INTERFACE LINK TIMING CHARACTERISTICS
t_D-LMFC	SYSREF to LMFC delay	Functional delay between SYSREF assertion latched and LMFC frame boundary. Depends on CLKDIV setting
		CLKDIV = 1		4		CLKIN cycles
		CLKDIV = 1		4		Frame clock cycles
		CLKDIV = 2		10		CLKIN cycles
		CLKDIV = 2		5		Frame clock cycles
		CLKDIV = 4		18		CLKIN cycles
		CLKDIV = 4		4.5		Frame clock cycles
t_D-K28	LMFC to K28.5 delay	Functional delay between the start of the first K28.5 frame during code group synchronization at the serial output and the preceding LMFC frame boundary	5.6	6.6	7.6	Frame clock cycles
t_D-ILA	LMFC to ILA delay	Functional delay between the start of the first ILA frame during initial lane synchronization at the serial output and the preceding LMFC frame boundary	5.6	6.6	7.6
t_D-DATA	LMFC to valid data delay	Functional delay between the start of the first valid data frame at the serial output and the preceding LMFC frame boundary	5.6	6.6	7.6
t_S-SYNCb-F	SYNCb setup time	Required SYNCb setup time-relative to the internal LMFC boundary⁽²⁾		3		Frame clock cycles
t_H-SYNCb-F	SYNCb hold time	Required SYNCb hold time relative to the internal LMFC boundary⁽²⁾		0
t_H-SYNCb	SYNCb assertion hold time	Required SYNCb hold time after assertion before de-assertion to initiate a link resynchronization		4
t_ILA	ILA duration	Duration of the ILA sequence		4		Multi-frame clock cycles
SERIAL OUTPUT DATA TIMING CHARACTERISTICS
F_SR	Serial bit rate		1		5.0	Gb/s
UI	Unit interval	5.0 Gb/s data rate		200		ps
t_R, t_F	Rise/fall times	5.0 Gb/s data rate, default values for VOD and DEM		43		ps
DJ	Deterministic jitter	Includes periodic jitter (PJ), data dependent jitter (DDJ), duty cycle distortion (DCD), and inter-symbol interference (ISI); 5.0 Gb/s data rate		0.049		p-p UI
DJ	Deterministic jitter			9.82		p-p ps
RJ	Random jitter	Assumes BER of 1e-15 (Q = 15.88); 5.0 Gb/s data rate		0.119		p-p UI
RJ	Random jitter	Assumes BER of 1e-15 (Q = 15.88); 5.0 Gb/s data rate		1.50		rms ps
TJ	Total jitter	Sum of DJ and RJ, assumes BER of 1e-15 (Q = 15.88); 5.0 Gb/s data rate		0.169		p-p UI
TJ	Total jitter			33.6		p-p ps
SPI BUS TIMING CHARACTERISTICS⁽³⁾
ƒ_SCLK	Serial clock frequency	f_SCLK = 1 / t_P			20	MHz
t_PH	SCLK pulse width – high		6			ns
t_PL	SCLK pulse width – low		7			ns
t_SSU	SDI input data setup time		3			ns
t_SH	SDI input data hold time		1			ns
t_ODZ	SDO output data driven-to-3-state time				10	ns
t_OZD	SDO output data 3-state-to-driven time				25	ns
t_OD	SDO output data delay time				25	ns
t_CSS	CSB setup time		3			ns
t_CSH	CSB hold time		1			ns
t_IAG	Inter-access gap	Minimum time CSB must be de-asserted between accesses	1			ns

(1) The SDO/OVR pin is configured in over-range output mode.

(2) The SYNCb setup and hold times determine the multi-frame after which the ILA is initiated but meeting the setup and hold times are not required to achieve deterministic latency.

(3) All timing specifications for the SPI given for V_SPI = 1.8-V logic levels and a 5-pF capacitive load on the SDO pin. Timing specification require larger margins for V_SPI= 1.2 V. The serial bit rate of the SPI should be limited to 10 Mb/s or lower for V_SPI = 1.2-V logic.

Figure 1. Sample Timing Diagram

Figure 2. Overrange (OVR) Timing Diagram

Figure 3. SPI Timing Diagram