ZHCSE48B September   2015  – January 2019 ADC31JB68

PRODUCTION DATA.  

  1. 1 特性
    1. 18 英寸、5 密耳输出端的传输眼图。5Gb/s、带优化型去加重功能的 FR4 微带迹线
  2. 2 应用
  3. 3 说明
    1.     –1dBFS、450MHz 输入时的频谱
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Converter Performance
    6. 6.6 Electrical Characteristics: Power Supply
    7. 6.7 Electrical Characteristics: Interface
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Interface Circuits
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs and Input Buffer
      2. 8.3.2  Amplitude and Phase Imbalance Correction
      3. 8.3.3  Over-Range Detection
      4. 8.3.4  Input Clock Divider
      5. 8.3.5  SYSREF Detection Gate
      6. 8.3.6  Serial Differential Output Drivers
        1. 8.3.6.1 De-Emphasis Equalization
        2. 8.3.6.2 Serial Lane Inversion
      7. 8.3.7  ADC Core Calibration
      8. 8.3.8  Data Format
      9. 8.3.9  JESD204B Supported Features
      10. 8.3.10 JESD204B Interface
      11. 8.3.11 Transport Layer Configuration
        1. 8.3.11.1 Lane Configuration
        2. 8.3.11.2 Frame Format
        3. 8.3.11.3 ILA Information
      12. 8.3.12 Test Pattern Sequences
      13. 8.3.13 JESD204B Link Initialization
        1. 8.3.13.1 Frame Alignment
        2. 8.3.13.2 Code Group Synchronization
      14. 8.3.14 SPI
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down and Sleep Modes
    5. 8.5 Register Map
      1. 8.5.1 Register Descriptions
        1. 8.5.1.1  CONFIG_A (address = 0x0000) [reset = 0x3C]
          1. Table 6. CONFIG_A
        2. 8.5.1.2  DEVICE CONFIG (address = 0x0002) [reset = 0x00]
          1. Table 7. DEVICE CONFIG
        3. 8.5.1.3  CHIP_TYPE (address = 0x0003 ) [reset = 0x03]
          1. Table 8. CHIP_TYPE
        4. 8.5.1.4  CHIP_ID (address = 0x0005, 0x0004) [reset = 0x00, 0x1B]
          1. Table 9. CHIP_ID
        5. 8.5.1.5  CHIP_VERSION (address =0x0006) [reset = 0x00]
          1. Table 10. CHIP_VERSION
        6. 8.5.1.6  VENDOR_ID (address = 0x000D, 0x000C) [reset = 0x04, 0x51]
          1. Table 11. VENDOR_ID
        7. 8.5.1.7  SPI_CFG (address = 0x0010 ) [reset = 0x01]
          1. Table 12. SPI_CFG
        8. 8.5.1.8  OM1 (Operational Mode 1) (address = 0x0012) [reset = 0xC1]
          1. Table 13. OM1 (Operational Mode 1)
        9. 8.5.1.9  OM2 (Operational Mode 2) (address = 0x0013) [reset = 0x20]
          1. Table 14. OM2 (Operational Mode 2)
        10. 8.5.1.10 IMB_ADJ (Imbalance Adjust) (address = 0x0014) [reset = 0x00]
          1. Table 15. IMB_ADJ (Imbalance Adjust)
        11. 8.5.1.11 OVR_EN (Over-Range Enable) (address = 0x003A) [reset = 0x00]
          1. Table 16. OVR_EN (Over-Range Enable)
        12. 8.5.1.12 OVR_HOLD (Over-Range Hold) (address = 0x003B) [reset = 0x00]
          1. Table 17. OVR_HOLD (Over-Range Hold)
        13. 8.5.1.13 OVR_TH (Over-Range Threshold) (address = 0x003C) [reset = 0x00]
          1. Table 18. OVR_TH (Over-Range Threshold)
        14. 8.5.1.14 DC_MODE (DC Offset Correction Mode) (address = 0x003D) [reset = 0x00]
          1. Table 19. DC_MODE (DC Offset Correction Mode)
        15. 8.5.1.15 SER_CFG (Serial Lane Transmitter Configuration) (address = 0x0047) [reset = 0x00]
          1. Table 20. SER_CFG (Serial Lane Transmitter Configuration)
        16. 8.5.1.16 JESD_CTRL1 (JESD Configuration Control 1) (address = 0x0060) [reset = 0x7F]
          1. Table 21. JESD_CTRL1 (JESD Configuration Control 1)
        17. 8.5.1.17 JESD_CTRL2 (JESD Configuration Control 2) (address = 0x0061) [reset = 0x00]
          1. Table 22. JESD_CTRL2 (JESD Configuration Control 2)
        18. 8.5.1.18 JESD_RSTEP (JESD Ramp Pattern Step) (address = 0x0063, 0x0062) [reset = 0x00, 0x01]
          1. Table 23. JESD_RSTEP (JESD Ramp Pattern Step)
        19. 8.5.1.19 SER_INV (Serial Lane Inversion Control) (address = 0x0064) [reset = 0x00]
          1. Table 24. SER_INV (Serial Lane Inversion Control)
        20. 8.5.1.20 JESD_STATUS (JESD Link Status) (address = 0x006C) [reset = N/A]
          1. Table 25. JESD_STATUS (JESD Link Status)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Optimizing Converter Performance
        1. 9.1.1.1 Internal Noise Sources
        2. 9.1.1.2 External Noise Sources
      2. 9.1.2 Analog Input Considerations
        1. 9.1.2.1 Differential Analog Inputs and Full Scale Range
        2. 9.1.2.2 Analog Input Network Model
        3. 9.1.2.3 Input Bandwidth
        4. 9.1.2.4 Driving the Analog Input
        5. 9.1.2.5 Clipping and Over-Range
      3. 9.1.3 CLKIN, SYSREF, and SYNCb Input Considerations
        1. 9.1.3.1 Driving the CLKIN+ and CLKIN– Input
        2. 9.1.3.2 Driving the SYSREF Input
        3. 9.1.3.3 SYSREF Signaling
        4. 9.1.3.4 SYSREF Timing
        5. 9.1.3.5 Effectively Using the Detection Gate Feature
        6. 9.1.3.6 Driving the SYNCb Input
      4. 9.1.4 Output Serial Interface Considerations
        1. 9.1.4.1 Output Serial-Lane Interface
        2. 9.1.4.2 Voltage Swing and De-Emphasis Optimization
        3. 9.1.4.3 Minimizing EMI
      5. 9.1.5 JESD204B System Considerations
        1. 9.1.5.1 Frame and LMFC Clock Alignment Procedure
        2. 9.1.5.2 Link Interruption
        3. 9.1.5.3 Clock Configuration Examples
      6. 9.1.6 SPI
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Design
    2. 10.2 Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 相关文档　
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.7 Electrical Characteristics: Interface

typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500 MSPS, 50% clock duty cycle, VA3.0 = 3 V; VA1.8 = 1.8 V; VA1.2 = VACLK1.2 = 1.2 V; –1 dBFS differential input, and R(term) = 100 Ω (unless otherwise noted) (see the Interface Circuits section)
PARAMETER NOTES MIN TYP MAX UNIT
ANALOG INPUTS (VIN+, VIN-)
V(FSR) Full-scale range voltage Differential peak-to-peak 1.7 V
VCM Nominal input common-mode voltage 1.6 V
ΔVCM Maximum input common mode voltage range VCM ± 0.05 V
RIN Input termination resistance Differential resistance at dc 190 Ω
CIN Input capacitance Differential 4.6 pF
INPUT COMMON MODE REFERENCE (VCM)
V(VCM) Common-mode reference voltage output 1.6 V
I(VCM) Maximum VCM pin current load 1 mA
CLOCK INPUT (CLKIN+, CLKIN-)
VID-MAX Maximum input voltage swing(1) Differential peak voltage 1000 mV
VID-MIN Minimum input voltage swing(1) Differential peak voltage 250 mV
dVSS/dt Input edge rate at zero crossing(1) Recommended minimum 5 V/ns
V(IS-BIAS) Input common-mode internal bias voltage(2)(1) 0.5 V
V(IS-IN) Externally applied common-mode voltage(1) DC-coupled interface 0.5 ± 0.1 V
Z(rdiff) Input termination resistance(2) Differential resistance at dc 100 Ω
Ztt Common-mode internal bias source impedance(2) 10 kΩ
CT Input capacitance(2) Differential 2 pF
SYSREF INPUT (SYSREF+, SYSREF-)
VID-MAX Maximum input voltage swing(1) Differential peak voltage 1000 mV
VID-MIN Minimum input voltage swing(1) Differential peak voltage 250 mV
V(IS-BIAS) Input common-mode internal bias voltage(1) 0.5 V
V(IS-IN) Externally applied common mode voltage(1) DC-coupled interface,
typical value depends on the configuration of the SYS_CM parameter		 V
SYS_CM = 00 0.5 ± 0.1
SYS_CM = 01 0.8 ± 0.2
SYS_CM = 10 1.25 ± 0.25
SYS_CM = 11 1.75 ± 0.25
Z(rdiff) Input termination resistance(2) Differential resistance at dc 100 Ω
Ztt Common-mode internal bias source impedance(2) 14 kΩ
CT Input capacitance(2) Differential 1 pF
SYNCb INPUT (SYNCb+, SYNCb-)
VID Input voltage swing(1) Differential peak voltage 350 mV
V(IS-IN) Externally applied common-mode voltage(1) DC-coupled interface 1.25 ± 0.75 V
Z(rdiff) Input termination resistance(2) Differential resistance at dc 100 Ω
CT Input capacitance(2) Differential 1 pF
SERDES OUTPUT (SO0+/-, SO1+/-) Meets JESD204B LV-OIF-11G-SR Standard
VOD Output differential voltage(3) Differential peak-peak voltage,
de-emphasis disabled (DEM = 0)		 mV
VOD = 0 400
VOD = 1 470
VOD = 2 540
VOD = 3 610
VOD = 4 670
VOD = 5 740
VOD = 6 790
VOD = 7 840
R(deepm) Transmitter de-emphasis range Configurable via SPI, VOD configured to 4 dB
DEM=0 0.0
DEM=1 –0.8
DEM=2 –2.4
DEM=3 –3.8
DEM=4 –4.9
DEM=5 –6.3
DEM=6 –7.7
DEM=7 –10.3
ISC Transmitter short circuit current Transmitter terminals shorted to each other or ground, power on 23 mA
Z(ddiff) Differential output impedance(4) 100 Ω
RL(ddiff) Differential output return loss magnitude Relative to 100 Ω,
for frequencies from 100 MHz to 0.75 × baud rate; default VOD and DEM.		 –8.5 dB
SCLK, SDI, CSB INPUT
VIH Logical 1 input voltage Inputs are compatible with 1.2-V up to 3-V logic. 0.9 V
VIL Logical 0 input voltage 0.3 V
IIN0 Logic low input current 4 nA
IIN1 Logic high input current –8 nA
CIN Input capacitance 2 pF
SDO/OVR OUTPUT
VOH Logical 1 output voltage(5) VSPI = 1.2 V, 1.8 V, or 3 V, configurable via SPI VSPI – 0.2 VSPI(5) V
VOL Logical 0 output voltage(5) 0 0.3 V
+ISC Logic high short circuit current VSPI = 1.8 V 9 mA
–ISC Logic low short circuit current VSPI = 1.8 V –14 mA
(1) Specification applies to the electrical level diagram of Figure 26
(2) Specification applies to the electrical circuit diagram of Figure 27
(3) Specification applies to the electrical level diagram of Figure 28
(4) Specification applies to the electrical circuit diagram of Figure 29
(5) The SPI_CFG register must be changed to a supported output logic level after power up and before a SPI read command is executed. Until that time, the output voltage on SDO/OVR may be as high as the VA3.0 supply during a SPI read command. The SDO/OVR output is high-Z at all times except during a read command.