ZHCSEE8B December   2015  – April 2017 ADC14X250

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Static Converter Performance
    6. 6.6  Electrical Characteristics: Dynamic Converter Performance
    7. 6.7  Electrical Characteristics: Power Supply
    8. 6.8  Electrical Characteristics: Analog Interface
    9. 6.9  Digital Input Characteristics
    10. 6.10 Electrical Characteristics: Serial Data Output Interface
    11. 6.11 Electrical Characteristics: Digital Input
    12. 6.12 Timing Requirements
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 JESD204B Interface Functional Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Amplitude and Phase Imbalance Correction of Differential Analog Input
      2. 8.3.2  Input Clock Divider
      3. 8.3.3  SYSREF Offset Feature and Detection Gate
      4. 8.3.4  DC Offset Correction
      5. 8.3.5  Serial Differential Output Drivers
        1. 8.3.5.1 De-Emphasis Equalization
      6. 8.3.6  ADC Core Calibration
      7. 8.3.7  Data Format
      8. 8.3.8  JESD204B Supported Features
      9. 8.3.9  Transport Layer Configuration
        1. 8.3.9.1 Lane Configuration
        2. 8.3.9.2 Frame Format
        3. 8.3.9.3 ILA Information
      10. 8.3.10 Test Pattern Sequences
      11. 8.3.11 JESD204B Link Initialization
        1. 8.3.11.1 Frame Alignment
        2. 8.3.11.2 Code Group Synchronization
      12. 8.3.12 Sync~ Signal Selection
      13. 8.3.13 SPI
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down and Sleep Modes
    5. 8.5 Register Map
      1. 8.5.1 Register Descriptions
        1. 8.5.1.1  CONFIG_A, [Address: 0x0000], [Default: 0x3C]
        2. 8.5.1.2  DEVICE CONFIG, [Address: 0x0002], [Default: 0x00]
        3. 8.5.1.3  CHIP_TYPE, [Address: 0x0003], [Default: 0x03]
        4. 8.5.1.4  CHIP_ID, [Address: 0x0005, 0x0004], [Default: 0x00, 0x01]
        5. 8.5.1.5  CHIP_VERSION, [Address: 0x0006], [Default: 0x00]
        6. 8.5.1.6  VENDOR_ID, [Address: 0x000D, 0x000C], [Default: 0x04, 0x51]
        7. 8.5.1.7  SPI_CFG, [Address: 0x0010], [Default: 0x01]
        8. 8.5.1.8  OM1 (Operational Mode 1), [Address: 0x0012], [Default: 0x81]
        9. 8.5.1.9  OM2 (Operational Mode 2), [Address: 0x0013], [Default: 0x20]
        10. 8.5.1.10 IMB_ADJ (Imbalance Adjust), [Address: 0x0014], [Default: 0x00]
        11. 8.5.1.11 DC_MODE (DC Offset Correction Mode), [Address: 0x003D], [Default: 0x00]
        12. 8.5.1.12 SER_CFG (Serial Lane Transmitter Configuration), [Address: 0x0047], [Default: 0x00]
        13. 8.5.1.13 JESD_CTRL1 (JESD Configuration Control 1) , [Address: 0x0060], [Default: 0x7D]
        14. 8.5.1.14 JESD_CTRL2 (JESD Configuration Control 2), [Address: 0x0061], [Default: 0x00]
        15. 8.5.1.15 JESD_RSTEP (JESD Ramp Pattern Step), [Addresses: 0x0063, 0x0062], [Default: 0x00, 0x01]
        16. 8.5.1.16 JESD_STATUS (JESD Link Status), [Address: 0x006C], [Default: N/A]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input Considerations
        1. 9.1.1.1 Differential Analog Inputs and Full Scale Range
        2. 9.1.1.2 Analog Input Network Model
        3. 9.1.1.3 Input Bandwidth
        4. 9.1.1.4 Driving the Analog Input
        5. 9.1.1.5 Clipping
      2. 9.1.2 CLKIN, SYSREF, and SYNCb Input Considerations
        1. 9.1.2.1 Driving the CLKIN+ and CLKIN- Input
        2. 9.1.2.2 Clock Noise and Edge Rate
        3. 9.1.2.3 Driving the SYSREF Input
        4. 9.1.2.4 SYSREF Signaling
        5. 9.1.2.5 SYSREF Timing
        6. 9.1.2.6 Effectively Using the SYSREF Offset and Detection Gate Features
        7. 9.1.2.7 Driving the SYNCb Input
      3. 9.1.3 Output Serial Interface Considerations
        1. 9.1.3.1 Output Serial-Lane Interface
        2. 9.1.3.2 Voltage Swing and De-Emphasis Optimization
        3. 9.1.3.3 Minimizing EMI
      4. 9.1.4 JESD204B System Considerations
        1. 9.1.4.1 Frame and LMFC Clock Alignment Procedure
        2. 9.1.4.2 Link Interruption
        3. 9.1.4.3 Clock Configuration Examples
        4. 9.1.4.4 Configuring the JESD204B Receiver
      5. 9.1.5 SPI
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Design Procedure
      3. 9.2.3 Application Performance Plot
      4. 9.2.4 Systems Example
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Design
    2. 10.2 Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Layout Example
      2. 11.1.2 Thermal Considerations
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 相关文档
        1. 12.1.1.1 技术规格定义
        2. 12.1.1.2 JESD204B 定义
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 修订历史记录

Changes from A Revision (March 2017) to B Revision

  • Changed VOH Test Conditions From: "Default VSPI = 1.8 V" To: "Default VSPI = 3 V" in Electrical Characteristics: Digital Input tableGo
  • Changed text From: "output 1.8 V logic levels..." To: "output 3 V logic levels..." in section SPIGo
  • Changed text From: "output 1.8 V logic levels..." To: "output 3 V logic levels..." in section SPIGo

Changes from * Revision (December 2015) to A Revision

  • Changed 0.1: 1.8 V (default) to 0.1: 3.0 V (default) in Table 13 Go
  • Changed 11: 3.0 V To: 11: 1.8 V in Table 13 Go