In space-constrained applications, PCB real estate often trumps correct component placement. While layout guidelines were provided in the previous section, this section specifically covers inductor placement in more detail. The inductor should be placed as close to the SW node as possible; this helps reduce parasitic resistances, inductances, and most importantly, parasitic capacitances.

Figure 10-1 SW Node Parasitic Capacitance

What happens if the SW node has too much parasitic capacitance? Two things:

1. The switching frequency decreases due to a higher RC constant, resulting in less current delivery to the load
2. The SW node stores charge in the parasitic capacitor, resulting in less current delivery to the load

The switching frequency changes as a result of the charging and discharging of the parasitic capacitor each cycle. Figure 10-2 shows how the current charge cycle of the inductor changes when parasitic capacitance is present.

Figure 10-2 Inductor Charging with Parasitic Capacitance

Figure 10-2 shows that the period of the inductor charge cycle increases with parasitic capacitance. This longer charge cycle results in a slower boost-switching frequency.

In addition to a slower switching frequency, the parasitic capacitance on the SW node consumes charge. If, for example, the DRVxxxx boost design normally supports 10-mA current and there is parasitic capacitance present, a significant portion – sometimes up to 1 mA of the current – can be consumed by the parasitic capacitance. This means that 10% of the current intended for the load is being consumed by the parasitic capacitance.

Both of these issues can have drastic effects on the output waveform. To identify switch node parasitic capacitance, look for continuous switching on the SW pin. During normal operation, the switching turns on and off depending on the current required; however, with parasitic capacitance the SW node often continuously switches to recover for lost switch cycles and current.