SBOA386B March   2020  – October 2023 INA180-Q1 , INA181-Q1 , INA185-Q1 , INA2180-Q1 , INA2181-Q1 , INA4180-Q1 , INA4181-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 INA180-Q1, SOT-23-5 Package
    2. 2.2 INA2180-Q1, VSSOP-8 Package
    3. 2.3 INA4180-Q1, TSSOP-14 Package
    4. 2.4 INA181-Q1, SOT-23-6 Package
    5. 2.5 INA2181-Q1, VSSOP-10 Package
    6. 2.6 INA4181-Q1, TSSOP-20 Package
    7. 2.7 INA181-Q1 and INA185-Q1, DCK Package
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 INA180-Q1, SOT-23-5 Package (Pinout A)
    2. 4.2 INA180-Q1, SOT-23-5 Package (Pinout B)
    3. 4.3 INA2180-Q1, VSSOP-8 Package
    4. 4.4 INA4180-Q1, TSSOP-14 Package
    5. 4.5 INA181-Q1, SOT-23-6 Package
    6. 4.6 INA2181-Q1, VSSOP-10 Package
    7. 4.7 INA4181-Q1, TSSOP-20 Package
    8. 4.8 INA181-Q1 and INA185-Q1, DCK Package
  7. 5Revision History

4.5 INA181-Q1, SOT-23-6 Package

INA181-Q1 Pin Diagram (SOT-23-6 Package) shows the INA181-Q1 pin diagram for the SOT-23-6 package. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the INA181-Q1 datasheet.


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Figure 4-5 INA181-Q1 Pin Diagram (SOT-23-6 Package)
Table 4-18 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
OUT 1 Output will be pulled down to GND and output current will be short circuit limited. When left in this configuration for a long time, under high supplies self-heating could cause die junction temperature to exceed 150°C. B
GND 2 Normal operation. D
IN+ 3 In high-side configuration, a short from the bus supply to GND will occur. B
IN- 4 In high-side configuration, a short from the bus supply to GND will occur (through RSHUNT). High current will flow from bus supply to GND. The shunt may be damaged. In low-side configuration, normal operation. B for high-side; D for low-side
REF 5 Normal operation if REF pin is at GND potential by design; otherwise the system measurement will be incorrect. D if REF=GND by design; B otherwise
VS 6 Power supply shorted to GND. B
Table 4-19 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
OUT 1 Output can be left open. There is no effect on the IC, but the output will not be measured. C
GND 2 When GND is floating, output will be incorrect as it is no longer referenced to GND. B
IN+ 3 Shunt resistor is not connected to amplifier. IN+ pin may float to an unknown value. Output will go to an unknown value not to exceed VS or GND. B
IN- 4 Shunt resistor is not connected to amplifier. IN- pin may float to an unknown value. Output will go to an unknown value not to exceed VS or GND. B
REF 5 Output common-mode voltage is not defined. Output will not maintain a linear relationship with differential input voltage. B
VS 6 No power to device. Device may be biased through inputs. Output will be incorrect and close to GND. B
Table 4-20 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No. Shorted to Description of Potential Failure Effect(s) Failure Effect Class
OUT 1 2 - GND Output will be pulled down to GND and output current will be short circuit limited. When left in this configuration for a long time, under high supplies self-heating could cause die junction temperature to exceed 150°C. B
GND 2 3 - IN+ In high-side configuration, a short from the bus supply to GND will occur. B
IN+ 3 4 - IN- Inputs shorted together, so no sense voltage applied. Output will stay close to REF potential. B
IN- 4 5 - REF In high-side configuration, REF shorted to bus supply. In low-side configuration, REF shorted to GND (normal operation if REF is at GND potential by design). A for high-side; B for low-side (D if REF=GND by design)
REF 5 6 - VS Normal operation if REF pin is at VS potential by design; otherwise the system measurement will be incorrect. D if REF=VS by design; B otherwise
VS 6 1 - OUT Output will be pulled to VS and output current will be short circuit limited. When left in this configuration for a long time, under high supplies self-heating could cause die junction temperature to exceed 150°C. B
Table 4-21 Pin FMA for Device Pins Short-Circuited to VS
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
OUT 1 Output will be pulled to VS and output current will be short circuit limited. When left in this configuration for a long time, under high supplies self-heating could cause die junction temperature to exceed 150°C. B
GND 2 Power supply shorted to GND. B
IN+ 3 In high-side configuration, device power supply shorted to bus supply. In low-side configuration, device power supply shorted to GND (through RSHUNT). A for high-side; B for low-side
IN- 4 In high-side configuration, device power supply shorted to bus supply (through RSHUNT). In low-side configuration, device power supply shorted to GND. A for high-side; B for low-side
REF 5 Normal operation if REF pin is at VS potential by design; otherwise the system measurement will be incorrect. D if REF=VS by design; B otherwise
VS 6 Normal operation. D