ZHCSPT6D July   2023  – June 2024 TPSM8287A06 , TPSM8287A10 , TPSM8287A12 , TPSM8287A15

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Device Options
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency DCS-Control Topology
      2. 7.3.2  Forced-PWM and Power-Save Modes
      3. 7.3.3  Precise Enable
      4. 7.3.4  Start-Up
      5. 7.3.5  Switching Frequency Selection
      6. 7.3.6  Output Voltage Setting
        1. 7.3.6.1 Output Voltage Setpoint
        2. 7.3.6.2 Output Voltage Range
        3. 7.3.6.3 Non-Default Output Voltage Setpoint
        4. 7.3.6.4 Dynamic Voltage Scaling (DVS)
      7. 7.3.7  Compensation (COMP)
      8. 7.3.8  Mode Selection / Clock Synchronization (MODE/SYNC)
      9. 7.3.9  Spread Spectrum Clocking (SSC)
      10. 7.3.10 Output Discharge
      11. 7.3.11 Undervoltage Lockout (UVLO)
      12. 7.3.12 Overvoltage Lockout (OVLO)
      13. 7.3.13 Overcurrent Protection
        1. 7.3.13.1 Cycle-by-Cycle Current Limiting
        2. 7.3.13.2 Hiccup Mode
        3. 7.3.13.3 Current-Limit Mode
      14. 7.3.14 Power Good (PG)
        1. 7.3.14.1 Power-Good Standalone, Primary Device Behavior
        2. 7.3.14.2 Power-Good Secondary Device Behavior
      15. 7.3.15 Remote Sense
      16. 7.3.16 Thermal Warning and Shutdown
      17. 7.3.17 Stacked Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset (POR)
      2. 7.4.2 Undervoltage Lockout
      3. 7.4.3 Standby
      4. 7.4.4 On
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 7.5.3 I2C Update Sequence
      4. 7.5.4 I2C Register Reset
  9. Device Registers
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Input Capacitors
        2. 9.2.2.2 Selecting the Target Loop Bandwidth
        3. 9.2.2.3 Selecting the Compensation Resistor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.2.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application Using Four TPSM8287Axx in Parallel Operation
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Selecting the Input Capacitors
        2. 9.3.2.2 Selecting the Target Loop Bandwidth
        3. 9.3.2.3 Selecting the Compensation Resistor
        4. 9.3.2.4 Selecting the Output Capacitors
        5. 9.3.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.3.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方产品免责声明
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Output Voltage Setpoint

During initialization, the device reads the state of the VSETx pins and selects the default output voltage according to Table 7-2. Note that the VSETx pins also select the I2C target address of the device and the setting of the VRANGE bits located in register CONTROL2. The VSETx pins are only read during a power cycle of VIN or by setting RESET = 1 through the I2C interface. Changing the configuration after VIN is present does not affect the content of the registers or the I2C address. Make sure that there is no stray current path connected to the VSETx pins and that the parasitic capacitance between the VSETx pins and GND is less than 100 pF. For proper operation, the input voltage needs to be at least 1.4 V above the selected output voltage.

Table 7-2 Start-Up Output Voltage and I2C Address

VSET3

VSET2

VSET1

I2C ADDRESS

VRANGE [1:0]

VOUT VOLTAGE

GND

GND

VIN

0x40

0b10

0.45 V

GND

VIN

GND

0x40

0b10

0.50 V

GND

VIN

VIN

0x40

0b10

0.55 V

VIN

GND

GND

0x40

0b10

0.60 V

VIN

GND

VIN

0x40

0b10

0.65 V

VIN

VIN

GND

0x40

0b10

0.70 V

VIN

VIN

VIN

0x40 (1)

0b10

0.75 V

47 kΩ to GND

GND

GND

0x41 (1)

0b11

0.80 V

47 kΩ to GND

GND

VIN

0x41

0b11

0.85 V

47 kΩ to GND

VIN

GND

0x41

0b11

0.90 V

47 kΩ to GND

VIN

VIN

0x41

0b11

0.95 V

47 kΩ to VIN

GND

GND

0x41

0b11

1.00 V

47 kΩ to VIN

GND

VIN

0x41 (1)

0b11

1.05 V

47 kΩ to VIN

VIN

GND

0x41 (1)

0b11

1.10 V

47 kΩ to VIN

VIN

VIN

0x41

0b11

1.15 V

GND

47 kΩ to GND

GND

0x42 (1)

0b11

1.20 V

GND

47 kΩ to GND

VIN

0x42

0b11

1.25 V

GND

47 kΩ to VIN

GND

0x42

0b11

1.30 V

GND

47 kΩ to VIN

VIN

0x42

0b11

1.35 V

VIN

47 kΩ to GND

GND

0x42

0b11

1.40 V

VIN

47 kΩ to GND

VIN

0x42

0b11

1.45 V

VIN

47 kΩ to VIN

GND

0x42

0b11

1.50 V

VIN

47 kΩ to VIN

VIN

0x42

0b11

1.55 V

GND

GND

47 kΩ to GND

0x43

0b11

1.60 V

GND

GND

47 kΩ to VIN

0x43

0b11

1.65 V

GND

VIN

47 kΩ to GND

0x43

0b11

1.70 V

GND

VIN

47 kΩ to VIN

0x43

0b11

1.75 V

VIN

GND

47 kΩ to GND

0x43

0b11

1.80 V

VIN

GND

47 kΩ to VIN

0x43

0b11

1.85 V

VIN

VIN

47 kΩ to GND

0x43

0b11

1.90 V

VIN

VIN

47 kΩ to VIN

0x43

0b11

1.95 V

47 kΩ to GND

47 kΩ to GND

GND

0x40

0b11

2.00 V

47 kΩ to GND

47 kΩ to GND

VIN

0x40

0b11

2.05 V

47 kΩ to GND

47 kΩ to VIN

GND

0x40

0b11

2.10 V

47 kΩ to GND

47 kΩ to VIN

VIN

0x40

0b11

2.15 V

47 kΩ to VIN

47 kΩ to GND

GND

0x40

0b11

2.20 V

47 kΩ to VIN

47 kΩ to GND

VIN

0x40

0b11

2.25 V

47 kΩ to VIN

47 kΩ to VIN

GND

0x40

0b11

2.30 V

47 kΩ to VIN

47 kΩ to VIN

VIN

0x40

0b11

2.35 V

47 kΩ to GND

GND

47 kΩ to GND

0x41

0b11

2.40 V

47 kΩ to GND

GND

47 kΩ to VIN

0x41

0b11

2.45 V

47 kΩ to GND

VIN

47 kΩ to GND

0x41

0b11

2.50 V

47 kΩ to GND

VIN

47 kΩ to VIN

0x41

0b11

2.55 V

47 kΩ to VIN

GND

47 kΩ to GND

0x41

0b11

2.60 V

47 kΩ to VIN

GND

47 kΩ to VIN

0x41

0b11

2.65 V

47 kΩ to VIN

VIN

47 kΩ to GND

0x41

0b11

2.70 V

47 kΩ to VIN

VIN

47 kΩ to VIN

0x41

0b11

2.75 V

GND

47 kΩ to GND

47 kΩ to GND

0x42

0b11

2.80 V

GND

47 kΩ to GND

47 kΩ to VIN

0x42

0b11

2.85 V

GND

47 kΩ to VIN

47 kΩ to GND

0x42

0b11

2.90 V

GND

47 kΩ to VIN

47 kΩ to VIN

0x42

0b11

2.95 V

VIN

47 kΩ to GND

47 kΩ to GND

0x42

0b11

3.00 V

VIN

47 kΩ to GND

47 kΩ to VIN

0x42

0b11

3.05 V

VIN

47 kΩ to VIN

47 kΩ to GND

0x42

0b11

3.10 V

VIN

47 kΩ to VIN

47 kΩ to VIN

0x42

0b11

3.15 V

47 kΩ to GND

47 kΩ to GND

47 kΩ to GND

0x43

0b11

3.20 V

47 kΩ to GND

47 kΩ to GND

47 kΩ to VIN

0x43

0b11

3.25 V

47 kΩ to GND

47 kΩ to VIN

47 kΩ to GND

0x43

0b11

3.30 V

47 kΩ to GND

47 kΩ to VIN

47 kΩ to VIN

0x43

0b11

3.35 V

47 kΩ to VIN

47 kΩ to GND

47 kΩ to GND

0x44

0b10

0.75 V

GND

GND

GND

0x40

0b11

0.80 V

47 kΩ to VIN

47 kΩ to GND

47 kΩ to VIN

0x44

0b11

1.05 V

47 kΩ to VIN

47 kΩ to VIN

47 kΩ to GND

0x44

0b11

1.10 V

47 kΩ to VIN

47 kΩ to VIN

47 kΩ to VIN

0x44

0b11

1.20 V

A second I2C address for the same output voltage is found at the bottom of this table

During start-up, the output voltage ramps up to the target value set by the VSETx pins before ramping up or down to any new value programmed to the device over the I2C interface. If the user programs new output voltage setpoints (VOUT[7:0]), output voltage range (VRANGE[1:0]), or soft-start time (SSTIME[1:0]) settings when the device has already begun the soft-start sequence, the device ignores the new values until the soft-start sequence is complete. When changing VOUT[7:0], VRAMP[1:0], or SSTIME[1:0] while EN is low, the device uses the new values the next time it is enabled.