ZHCSAI3E May   2012  – March 2017 TPS65131-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Conversion
      2. 8.3.2 Control
      3. 8.3.3 Output Rails Enable or Disable
      4. 8.3.4 Load Disconnect
      5. 8.3.5 Soft Start
      6. 8.3.6 Overvoltage Protection
      7. 8.3.7 Undervoltage Lockout
      8. 8.3.8 Overtemperature Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Save Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPS65131-Q1 With VPOS = 10.5 V, VNEG = -10 V
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Programming the Output Voltage
            1. 9.2.1.2.1.1 Boost Converter
            2. 9.2.1.2.1.2 Inverting Converter
          2. 9.2.1.2.2 Inductor Selection
          3. 9.2.1.2.3 Capacitor Selection
            1. 9.2.1.2.3.1 Input Capacitor
            2. 9.2.1.2.3.2 Output Capacitors
          4. 9.2.1.2.4 Rectifier Diode Selection
          5. 9.2.1.2.5 External P-MOSFET Selection
          6. 9.2.1.2.6 Stabilizing the Control Loop
            1. 9.2.1.2.6.1 Feedforward Capacitors
            2. 9.2.1.2.6.2 Compensation Capacitors
        3. 9.2.1.3 Analog Supply Input Filter
          1. 9.2.1.3.1 RC-Filter
          2. 9.2.1.3.2 LC-Filter
        4. 9.2.1.4 Thermal Information
        5. 9.2.1.5 Application Curves
      2. 9.2.2 TPS65131-Q1 With VPOS = 5.5 V, VNEG = -5 V
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curves
      3. 9.2.3 TPS65131-Q1 With VPOS = 15 V, VNEG = -15 V
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

24-pin VQFN With PowerPAD™ Package
RGE Package
(Bottom View)
TPS65131-Q1 pinout-bottom_SLVSBB2.gif
place
place
(Top View)
TPS65131-Q1 pinout-top_SLVSBB2.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AGND 19 — Analog ground pin
BSW 7 O Gate-control pin for external battery switch. This pin goes low when ENP is set high.
CN 18 I/O Compensation pin for inverting converter control
CP 21 I/O Compensation pin for boost converter control
ENN 10 I Enable pin for the negative-output voltage (0 V: disabled, VIN: enabled)
ENP 8 I Enable pin for the positive-output voltage (0 V: disabled, VIN: enabled)
FBN 16 I Feedback pin for the negative-output voltage divider
FBP 22 I Feedback pin for the positive-output voltage divider
INN 5, 6 O Inverting converter switch pin
INP 1, 24 O Boost converter switch pin
NC(1) 12, 20 — Not connected
OUTN 13, 14 I/O Inverting converter switch output
PGND 2, 3 — Power ground pin
PSN 11 I Power-save mode enable for inverter stage (0 V: disabled, VIN: enabled)
PSP 9 I Power-save mode enable for boost converter stage (0 V: disabled, VIN: enabled)
VIN 4 I Control supply input
VNEG 15 I Negative-output voltage-sense input
VPOS 23 I Positive-output voltage-sense input
VREF 17 O Reference output voltage. Bypass this pin with a 220-nF capacitor to ground. Connect the lower resistor of the negative-output voltage divider to this pin.
Thermal pad Thermal pad for thermal performance, connect to PGND(1)
(1) NC - No internal connection