ZHCSC57E November   2013  – December 2017 TPS56520 , TPS56720 , TPS56920 , TPS56C20

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
    1.     Device Images
      1.      典型应用电路
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 List of Devices
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 PWM Operation
      2. 9.3.2 PWM Frequency and Adaptive On-Time Control
      3. 9.3.3 VIN and Power VIN Terminals (VIN and PVIN)
      4. 9.3.4 Auto-Skip Eco-mode™ Control
      5. 9.3.5 Soft Start and Pre-Biased Soft Start
      6. 9.3.6 Power Good
      7. 9.3.7 Overcurrent Protection
      8. 9.3.8 UVLO Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation at Light Loads
    5. 9.5 Programming
      1. 9.5.1 I2C Interface
      2. 9.5.2 I2C Protocol
      3. 9.5.3 I2C Chip Address Byte
    6. 9.6 Register Maps
      1. 9.6.1 I2C Register Address Byte
      2. 9.6.2 Output Voltage Registers
      3. 9.6.3 CheckSum Bit (VOUT Register Only)
      4. 9.6.4 Control Registers
      5. 9.6.5 Latchoff
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 TPS56520, TPS56720 and TPS56920, 5-A, 7-A, and 9-A Converter
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Output Voltage Resistors Selection
            1. 10.2.1.2.1.1 Output Filter Selection
          2. 10.2.1.2.2 Input Capacitor Selection
          3. 10.2.1.2.3 Bootstrap Capacitor Selection
          4. 10.2.1.2.4 VREG5 Capacitor Selection
      2. 10.2.2 TPS56520, TPS56720 and TPS56920 Application Performance Curves
      3. 10.2.3 TPS56C20 12-A Converter
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Design Procedure
        3. 10.2.3.3 TPS56C20 Application Performance Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 器件支持
      1. 13.1.1 开发支持
    2. 13.2 文档支持
      1. 13.2.1 相关文档
    3. 13.3 相关链接
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • PWP|20
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.3.5 Soft Start and Pre-Biased Soft Start

The soft start function is adjustable. When the EN terminal becomes high, 6-µA current begins charging the capacitor which is connected from the SS terminal to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 1. VFB voltage is 0.6 V and SS terminal source current is 6µA.

Equation 1. TPS56C20 TPS56920 TPS56720 TPS56520 EQ2_tss_slvscb6.gif

The TPS56X20 contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than internal feedback voltage, VFB), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VOUT) starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation. When pre-biased conditions exist, it is recommended to disable the device by pulling the EN terminal to ground.