As soon as the EN/PG pin is set high and input PWM pulses are initiated (see Note below). The dead-time control circuit ensures that there is no overlapping between UGATE and LGATE drive outputs to eliminate shoot through current through the external power FETs. Additionally to operate under periodical pulse sequencing, the TPS28225-Q1 has a self-adjustable PWM 3-state input circuit. The 3-state circuit sets both gate drive outputs low, and thus turns the external power FETs OFF if the input signal is in a high impedance state for at least 250 ns typical. At this condition, the PWM input voltage level is defined by the internal 27-kΩ to 13-kΩ resistor divider shown in the block diagram. This resistor divider forces the input voltage to move into the 3-state window. Initially the 3-state window is set between 1.0-V and 2.0-V thresholds. The lower threshold of the 3-state window is always fixed at about 1.0 V. The higher threshold is adjusted to about 75% of the input signal amplitude. The self-adjustable upper threshold allows shorter delay if the input signal enters the 3-state window while the input signal was high, thus keeping the high-side power FET in ON state just slightly longer than 250 ns time constant set by an internal 3-state timer. Both modes of operation, PWM input pulse sequencing and the 3-state condition, are illustrated in the timing diagrams shown in Figure 6-1. The self-adjustable upper threshold allows operation in wide range amplitude of input PWM pulse signals. The waveforms in Figure 7-2 and Figure 7-3 illustrates the TPS28225-Q1 operation at normal and 3-state mode with the input pulse amplitudes 6 V and 2.5 V accordingly. After entering into the 3-state window and staying within the window for the hold-off time, the PWM input signal level is defined by the internal resistor divider and, depending on the input pulse amplitude, can be pulled up above the normal PWM pulse amplitude (Figure 7-3) or down below the normal input PWM pulse (Figure 7-2).

Figure 7-2 6-V Amplitude PWM Pulse (TPS28225-Q1)

Figure 7-3 2.5-V Amplitude PWM Pulse (TPS28225-Q1)

In the case where the low-side MOSFET of a buck converter stays on during shutdown, the 3-state feature can be fused to avoid negative resonant voltage across the output capacitor. This feature also can be used during start up with a pre-biased output in the case where pulling the output low during the startup is not allowed due to system requirements. If the system controller does not have the 3-state feature and never goes into the high-impedance state, then setting the EN/PG signal low will keep both gate drive outputs low and turn both low- and high-side MOSFETs OFF during the shut down and start up with the pre-biased output.

The self-adjustable input circuit accepts wide range of input pulse amplitudes (2 V up to 13.2 V) allowing use of a variety of controllers with different outputs including logic level. The wide PWM input voltage allows some flexibility if the driver is used in secondary side synchronous rectifier circuit. The operation of the TPS28225-Q1 with a 12-V input PWM pulse amplitude, and with V_DD = 7.2 V and V_DD = 5 V respectively is shown in Figure 7-4 and Figure 7-5.

Figure 7-4 12-V PWM Pulse at V_DD = 7.2 V

Figure 7-5 12-V PWM Pulse at V_DD = 5 V