ZHCSGV1C June   2017  – March 2018 TPS25740B

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 VBUS Capacitance
      2. 8.1.2 USB Data Communications
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  ENSRC
      2. 8.3.2  USB Type-C CC Logic (CC1, CC2)
      3. 8.3.3  USB PD BMC Transmission (CC1, CC2, VTX)
      4. 8.3.4  USB PD BMC Reception (CC1, CC2)
      5. 8.3.5  Discharging (DSCG, VPWR)
        1. 8.3.5.1 Discharging after a Fault (VPWR)
      6. 8.3.6  Configuring Voltage Capabilities (HIPWR)
      7. 8.3.7  Configuring Power Capabilities (PSEL, PCTRL, HIPWR)
      8. 8.3.8  Gate Driver (GDNG, GDNS)
      9. 8.3.9  Fault Monitoring and Protection
        1. 8.3.9.1 Over/Under Voltage (VBUS)
        2. 8.3.9.2 Over-Current Protection (ISNS, VBUS)
        3. 8.3.9.3 System Fault Input (GD, VPWR)
      10. 8.3.10 Voltage Control (CTL1, CTL2,CTL3)
      11. 8.3.11 Sink Attachment Indicator (DVDD)
      12. 8.3.12 Power Supplies (VAUX, VDD, VPWR, DVDD)
      13. 8.3.13 Grounds (AGND, GND)
      14. 8.3.14 Output Power Supply (DVDD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
      2. 8.4.2 Checking VBUS at Start Up
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 System-Level ESD Protection
      2. 9.1.2 Using ENSRC to Enable the Power Supply upon Sink Attachment
      3. 9.1.3 Use of GD Internal Clamp
      4. 9.1.4 Resistor Divider on GD for Programmable Start Up
      5. 9.1.5 Selection of the CTL1, CTL2, and CTL3 Resistors (R(FBL1), R(FBL2), and R(FBL3))
      6. 9.1.6 Voltage Transition Requirements
      7. 9.1.7 VBUS Slew Control using GDNG C(SLEW)
      8. 9.1.8 Tuning OCP using RF and CF
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application, A/C Power Source (Wall Adapter)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power Pin Bypass Capacitors
          2. 9.2.1.2.2 Non-Configurable Components
          3. 9.2.1.2.3 Configurable Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Typical Application, D/C Power Source
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Power Pin Bypass Capacitors
          2. 9.2.2.2.2 Non-Configurable Components
          3. 9.2.2.2.3 Configurable Components
        3. 9.2.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 D/C Power Source (Power Hub)
      2. 9.3.2 A/C Power Source (Wall Adapter)
      3. 9.3.3 Dual-Port A/C Power Source (Wall Adaptor)
      4. 9.3.4 D/C Power Source (Power Hub with 3.3 V Rail)
  10. 10Power Supply Recommendations
    1. 10.1 VDD
    2. 10.2 VPWR
  11. 11Layout
    1. 11.1 Port Current Kelvin Sensing
    2. 11.2 Layout Guidelines
      1. 11.2.1 Power Pin Bypass Capacitors
      2. 11.2.2 Supporting Components
    3. 11.3 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.7 Switching Characteristics

Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65 V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND; VAUX, VTX, bypassed with 0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tVP Delay from enabling external NFET until under-voltage and OCP protection are enabled VBUS = GND 190 ms
tSTL Source settling time, time from CTL1, CTL2, or CTL3 being changed until a PS_RDY USB PD message is transmitted to inform the sink is may draw full current. (refer to USB PD in 文档支持) 260 ms
tSR Time that GDNG is disabled after a hard reset. This is tSrcRecover. (refer to USB PD in 文档支持) TJ > TJ1 765 ms
tHR Time after hard reset is transmitted until GDNG is disabled. This is tPSHardReset. (refer to USB PD in 文档支持) 30 ms
tCCDeb Time until ENSRC is pulled low after sink attachment, this is the USB Type-C required debounce time for attachment detection called tCCDebounce. (refer to USB Type-C in 文档支持) 185 ms
tST Delay after sink request is accepted until CTL1, CTL2, or CTL3 is changed. This is called tSnkTransition. (refer to USB PD in 文档支持) 30 ms
tFLT The time in between hard reset transmissions in the presence of a persistent supply fault. GD = GND or VPWR = GND, sink attached 1395 ms
tSH The time in between retries (hard reset transmissions) in the presence of a persistent VBUS short. VBUS = GND, sink attached 985 ms
tON The time from ENSRC being pulled low until a hard reset is transmitted. Designed to be greater than tSrcTurnOn. (refer to USB PD in 文档支持) GD = 0 V or VPWR = 0 V 600 ms
Retry interval if USB PD sink stops communicating without being removed or if sink does not communicate after a fault condition. Time GDNG remains enabled before a hard reset is transmitted. This is the tNoResponse time. (refer to USB PD in 文档支持) Sink attached 4.8 s
tDVDD Delay before DVDD is driven high After sink attached 5 ms
tGDoff Turnoff delay, time until V(GDNG) is below 10% of its initial value after the GD pin is low VGD: 5 V → 0 V in < 0.5 µs 5 µs
tFOVP Response time when VBUS exceeds the fast-OVP threshold VBUS ↑ to GDNG OFF
(V(GDNG) below 10% its initial value)		 30 µs
OCP large signal response time 5 A enabled, V(ISNS) -V(VBUS): 0 V → 42 mV measured to GDNG transition start 30 µs
Time until discharge is stopped after TJ1 is exceeded. 0 V ≤ V(DSCG) ≤ 25 V 10 µs
Digital output fall time V(PULLUP) = 1.8 V, CL = 10 pF,
R(PULLUP) = 10 kΩ, V(CTLx) or
V(ENSRC) : 70% VPULLUP → 30% VPULLUP 		20 300 ps
TPS25740B Fig_1_Timing_slvsdr6.gifFigure 1. Timing Illustration for tVP, tST and tSTL, After Sink Attachment Negotiation to 12 V Then Back to 5 V. V(SOVP) and V(SUVP) are Disabled Around Voltage Transitions.
TPS25740B Fig_2_Timing_slvsdr6.gifFigure 2. Timing Illustration for tHR and tSR, After Sink Attachment with Persistent TJ > TJ1
TPS25740B Fig_3_Timing_slvsdr6.gifFigure 3. Timing Illustration for tCcDeb and tVP, Under Persistent Fault Condition
TPS25740B Fig_4_Timing_slvsdr6.gifFigure 4. Timing Illustration for tSH and tVP, with VBUS Shorted to Ground
TPS25740B Fig_5_Timing_slvsdr6.gifFigure 5. Timing Illustration for tON
TPS25740B Fig_6_Timing_slvsdr6.gifFigure 6. Timing Illustration for tON
TPS25740B HardResetRx_slvsdr6.gifFigure 7. Timing Diagram for ENSRC and GDNG After Receiving a Hard Reset
TPS25740B HardResetTx_slvsdr6.gifFigure 8. Timing Diagram for ENSRC and GDNG After Transmitting a Hard Reset