ZHCSIV8B January   2010  – October 2018 TLV320DAC3101

PRODUCTION DATA.  

  1. 1介绍
    1. 1.1 特性
    2. 1.2 应用范围
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Attributes
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics
    6. 4.6  Power Dissipation Ratings
    7. 4.7  I2S, LJF, and RJF Timing in Slave Mode
    8. 4.8  DSP Timing in Master Mode
    9. 4.9  DSP Timing in Slave Mode
    10. 4.10 I2C Interface Timing
    11. 4.11 Typical Characteristics
      1. 4.11.1 DAC Performance
      2. 4.11.2 Class-D Speaker Driver Performance
      3. 4.11.3 Analog Bypass Performance H
      4. 4.11.4 MICBIAS Performance H
  5. 5Parameter Measurement Information
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Supply Sequence
      2. 6.3.2  Reset
      3. 6.3.3  Device Start-Up Lockout Times
      4. 6.3.4  PLL Start-Up
      5. 6.3.5  Power-Stage Reset
      6. 6.3.6  Software Power Down
      7. 6.3.7  Audio Analog I/O
      8. 6.3.8  Digital Processing Low-Power Modes
        1. 6.3.8.1 DAC Playback on Headphones, Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
        2. 6.3.8.2 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
        3. 6.3.8.3 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
        4. 6.3.8.4 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
        5. 6.3.8.5 DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
        6. 6.3.8.6 DAC Playback on Line Out (10 k-Ω load), Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3 V, HPVDD = 3 V
      9. 6.3.9  Analog Signals
        1. 6.3.9.1 MICBIAS
        2. 6.3.9.2 Analog Inputs AIN1 and AIN2
      10. 6.3.10 Audio DAC and Audio Analog Outputs
        1. 6.3.10.1  DAC
          1. 6.3.10.1.1 DAC Processing Blocks
          2. 6.3.10.1.2 DAC Processing Blocks — Details
            1. 6.3.10.1.2.1  Three Biquads, Filter A
            2. 6.3.10.1.2.2  Six Biquads, First-Order IIR, DRC, Filter A or B
            3. 6.3.10.1.2.3  Six Biquads, First-Order IIR, Filter A or B
            4. 6.3.10.1.2.4  IIR, Filter B or C
            5. 6.3.10.1.2.5  Four Biquads, DRC, Filter B
            6. 6.3.10.1.2.6  Four Biquads, Filter B
            7. 6.3.10.1.2.7  Four Biquads, First-Order IIR, DRC, Filter C
            8. 6.3.10.1.2.8  Four Biquads, First-Order IIR, Filter C
            9. 6.3.10.1.2.9  Two Biquads, 3D, Filter A
            10. 6.3.10.1.2.10 Five Biquads, DRC, 3D, Filter A
            11. 6.3.10.1.2.11 Five Biquads, DRC, 3D, Beep Generator, Filter A
          3. 6.3.10.1.3 DAC User-Programmable Filters
            1. 6.3.10.1.3.1 First-Order IIR Section
            2. 6.3.10.1.3.2 Biquad Section
          4. 6.3.10.1.4 DAC Interpolation Filter Characteristics
            1. 6.3.10.1.4.1 Interpolation Filter A
            2. 6.3.10.1.4.2 Interpolation Filter B
            3. 6.3.10.1.4.3 Interpolation Filter C
        2. 6.3.10.2  DAC Digital-Volume Control
        3. 6.3.10.3  Volume Control Pin
        4. 6.3.10.4  Dynamic Range Compression
          1. 6.3.10.4.1 DRC Threshold
          2. 6.3.10.4.2 DRC Hysteresis
          3. 6.3.10.4.3 DRC Hold Time
          4. 6.3.10.4.4 DRC Attack Rate
          5. 6.3.10.4.5 DRC Decay Rate
          6. 6.3.10.4.6 Example Setup for DRC
        5. 6.3.10.5  Headphone Detection
        6. 6.3.10.6  Interrupts
        7. 6.3.10.7  Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25)
        8. 6.3.10.8  Programming DAC Digital Filter Coefficients
        9. 6.3.10.9  Updating DAC Digital Filter Coefficients During PLAY
        10. 6.3.10.10 Digital Mixing and Routing
        11. 6.3.10.11 Analog Audio Routing
          1. 6.3.10.11.1 Analog Output Volume Control
          2. 6.3.10.11.2 Headphone Analog-Output Volume Control
          3. 6.3.10.11.3 Class-D Speaker Analog Output Volume Control
        12. 6.3.10.12 Analog Outputs
          1. 6.3.10.12.1 Headphone Drivers
          2. 6.3.10.12.2 Speaker Drivers
        13. 6.3.10.13 Audio-Output Stage-Power Configurations
        14. 6.3.10.14 DAC Setup
        15. 6.3.10.15 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs
      11. 6.3.11 CLOCK Generation and PLL
        1. 6.3.11.1 PLL
      12. 6.3.12 Timer
      13. 6.3.13 Digital Audio and Control Interface
        1. 6.3.13.1 Digital Audio Interface
          1. 6.3.13.1.1 Right-Justified Mode
          2. 6.3.13.1.2 Left-Justified Mode
          3. 6.3.13.1.3 I2S Mode
          4. 6.3.13.1.4 DSP Mode
        2. 6.3.13.2 Primary and Secondary Digital Audio Interface Selection
        3. 6.3.13.3 Control Interface
          1. 6.3.13.3.1 I2C Control Mode
    4. 6.4 Register Map
      1. 6.4.1 Register Map
      2. 6.4.2 Registers
        1. 6.4.2.1 Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags, Interrupts, and GPIOs
          1. Table 6-31 Page 0 / Register 0 (0x00): Page Control Register
          2. Table 6-32 Page 0 / Register 1 (0x01): Software Reset
          3. Table 6-33 Page 0 / Register 2 (0x02): Reserved
          4. Table 6-34 Page 0 / Register 3 (0x03): OT FLAG
          5. Table 6-35 Page 0 / Register 4 (0x04): Clock-Gen Muxing
          6. Table 6-36 Page 0 / Register 5 (0x05): PLL P and R Values
          7. Table 6-37 Page 0 / Register 6 (0x06): PLL J-Value
          8. Table 6-38 Page 0 / Register 7 (0x07): PLL D-Value MSB
          9. Table 6-39 Page 0 / Register 8 (0x08): PLL D-Value LSB
          10. Table 6-40 Page 0 / Register 9 (0x09) and Page 0 / Register 10 (0x0A): Reserved
          11. Table 6-41 Page 0 / Register 11 (0x0B): DAC NDAC_VAL
          12. Table 6-42 Page 0 / Register 12 (0x0C): DAC MDAC_VAL
          13. Table 6-43 Page 0 / Register 13 (0x0D): DAC DOSR_VAL MSB
          14. Table 6-44 Page 0 / Register 14 (0x0E): DAC DOSR_VAL LSB
          15. Table 6-45 Page 0 / Register 15 (0x0F) through Page 0 / Register 24 (0x18): Reserved
          16. Table 6-46 Page 0 / Register 25 (0x19): CLKOUT MUX
          17. Table 6-47 Page 0 / Register 26 (0x1A): CLKOUT M_VAL
          18. Table 6-48 Page 0 / Register 27 (0x1B): Codec Interface Control 1
          19. Table 6-49 Page 0 / Register 28 (0x1C): Data-Slot Offset Programmability
          20. Table 6-50 Page 0 / Register 29 (0x1D): Codec Interface Control 2
          21. Table 6-51 Page 0 / Register 30 (0x1E): BCLK N_VAL
          22. Table 6-52 Page 0 / Register 31 (0x1F): Codec Secondary Interface Control 1
          23. Table 6-53 Page 0 / Register 32 (0x20): Codec Secondary Interface Control 2
          24. Table 6-54 Page 0 / Register 33 (0x21): Codec Secondary Interface Control 3
          25. Table 6-55 Page 0 / Register 34 (0x22): I2C Bus Condition
          26. Table 6-56 Page 0 / Register 35 (0x23) and Page 0 / Register 36 (0x24): Reserved
          27. Table 6-57 Page 0 / Register 37 (0x25): DAC Flag Register
          28. Table 6-58 Page 0 / Register 38 (0x26): DAC Flag Register
          29. Table 6-59 Page 0 / Register 39 (0x27): Overflow Flags
          30. Table 6-60 Page 0 / Register 40 (0x28) Through Page 0 / Register 43 (0x2B): Reserved
          31. Table 6-61 Page 0 / Register 44 (0x2C): DAC Interrupt Flags (Sticky Bits)
          32. Table 6-62 Page 0 / Register 45 (0x2D): Reserved
          33. Table 6-63 Page 0 / Register 46 (0x2E): Interrupt Flags—DAC
          34. Table 6-64 Page 0 / Register 47 (0x2F): Reserved
          35. Table 6-65 Page 0 / Register 48 (0x30): INT1 Control Register
          36. Table 6-66 Page 0 / Register 49 (0x31): INT2 Control Register
          37. Table 6-67 Page 0 / Register 50 (0x32): Reserved
          38. Table 6-68 Page 0 / Register 52 (0x34): Reserved
          39. Table 6-69 Page 0 / Register 53: Reserved
          40. Table 6-70 Page 0 / Register 54 (0x36): DIN (IN Pin) Control
          41. Table 6-71 Page 0 / Register 55 (0x37) through Page 0 / Register 59 (0x3B): Reserved
          42. Table 6-72 Page 0 / Register 60 (0x3C): DAC Processing Block Selection
          43. Table 6-73 Page 0 / Register 61 (0x3D)Through Page 0 / Register 62: Reserved
          44. Table 6-74 Page 0 / Register 63 (0x3F): DAC Data-Path Setup
          45. Table 6-75 Page 0 / Register 64 (0x40): DAC Volume Control
          46. Table 6-76 Page 0 / Register 65 (0x41): DAC Left Volume Control
          47. Table 6-77 Page 0 / Register 66 (0x42): DAC Right Volume Control
          48. Table 6-78 Page 0 / Register 67 (0x43): Headset Detection
          49. Table 6-79 Page 0 / Register 68 (0x44): DRC Control 1
          50. Table 6-80 Page 0 / Register 69 (0x45): DRC Control 2
          51. Table 6-81 Page 0 / Register 70 (0x46): DRC Control 3
          52. Table 6-82 Page 0 / Register 71 (0x47): Left Beep Generator
          53. Table 6-83 Page 0 / Register 72 (0x48): Right Beep Generator
          54. Table 6-84 Page 0 / Register 73 (0x49): Beep Length MSB
          55. Table 6-85 Page 0 / Register 74 (0x4A): Beep-Length Middle Bits
          56. Table 6-86 Page 0 / Register 75 (0x4B): Beep Length LSB
          57. Table 6-87 Page 0 / Register 76 (0x4C): Beep Sin(x) MSB
          58. Table 6-88 Page 0 / Register 77 (0x4D): Beep Sin(x) LSB
          59. Table 6-89 Page 0 / Register 78 (0x4E): Beep Cos(x) MSB
          60. Table 6-90 Page 0 / Register 79 (0x4F): Beep Cos(x) LSB
          61. Table 6-91 Page 0 / Register 80 (0x50) Through Page 0 / Register 115 (0x73): Reserved
          62. Table 6-92 Page 0 / Register 116 (0x74): VOL/MICDET-Pin SAR ADC — Volume Control
          63. Table 6-93 Page 0 / Register 117 (0x75): VOL/MICDET-Pin Gain
          64. Table 6-94 Page 0 / Register 118 (0x76) Through Page 0 / Register 127 (0x7F): Reserved
        2. 6.4.2.2 Control Registers, Page 1: DAC, Power-Controls, and MISC Logic-Related Programmability
          1. Table 6-95  Page 1 / Register 0 (0x00): Page Control Register
          2. Table 6-96  Page 1 / Register 1 (0x01) Through Page 1 / Register 29 (0x1D): Reserved
          3. Table 6-97  Page 1 / Register 30 (0x1E): Headphone and Speaker Amplifier Error Control
          4. Table 6-98  Page 1 / Register 31 (0x1F): Headphone Drivers
          5. Table 6-99  Page 1 / Register 32 (0x20): Class-D Speaker Amplifier
          6. Table 6-100 Page 1 / Register 33 (0x21): HP Output Drivers POP Removal Settings
          7. Table 6-101 Page 1 / Register 34 (0x22): Output Driver PGA Ramp-Down Period Control
          8. Table 6-102 Page 1 / Register 35 (0x23): DAC_L and DAC_R Output Mixer Routing
          9. Table 6-103 Page 1 / Register 36 (0x24): Left Analog Volume to HPL
          10. Table 6-104 Page 1 / Register 37 (0x25): Right Analog Volume to HPR
          11. Table 6-105 Page 1 / Register 38 (0x26): Left Analog Volume to SPL
          12. Table 6-106 Page 1 / Register 39 (0x27): Right Analog Volume to SPR
          13. Table 6-107 Page 1 / Register 40 (0x28): HPL Driver
          14. Table 6-108 Page 1 / Register 41 (0x29): HPR Driver
          15. Table 6-109 Page 1 / Register 42 (0x2A): SPL Driver
          16. Table 6-110 Page 1 / Register 43 (0x2B): SPR Driver
          17. Table 6-111 Page 1 / Register 44 (0x2C): HP Driver Control
          18. Table 6-112 Page 1 / Register 45 (0x2D): Reserved
          19. Table 6-113 Page 1 / Register 46 (0x2E): MICBIAS
          20. Table 6-114 Page 1 / Register 50 (0x32): Input CM Settings
          21. Table 6-115 Page 1 / Register 51 (0x33) Through Page 1 / Register 127 (0x7F): Reserved
        3. 6.4.2.3 Control Registers, Page 3: MCLK Divider for Programmable Delay Timer
          1. Table 6-116 Page 3 / Register 0 (0x00): Page Control Register
          2. Table 6-117 Page 3 / Register 16 (0x10): Timer Clock MCLK Divider
        4. 6.4.2.4 Control Registers, Page 8: DAC Programmable Coefficients RAM Buffer A (1:63)
          1. Table 6-118 Page 8 / Register 0 (0x00): Page Control Register
          2. Table 6-119 Page 8 / Register 1 (0x01): DAC Coefficient RAM Control
          3. Table 6-120 Page-8 DAC Buffer A Registers
        5. 6.4.2.5 Control Registers, Page 9: DAC Programmable Coefficients RAM Buffer A (65:127)
          1. Table 6-121 Page 9 / Register 0 (0x00): Page Control Register
          2. Table 6-122 Page-9 DAC Buffer A Registers
        6. 6.4.2.6 Control Registers, Page 12: DAC Programmable Coefficients RAM Buffer B (1:63)
          1. Table 6-1   Page 12 / Register 0 (0x00): Page Control Register
          2. Table 6-123 Page-12 AC Buffer B Registers
        7. 6.4.2.7 Control Registers, Page 13: DAC Programmable Coefficients RAM Buffer B (65:127)
          1. Table 6-2   Page 13 / Register 0 (0x00): Page Control Register
          2. Table 6-124 Page-13 DAC Buffer B Registers
  7. 7Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
  8. 8Power Supply Recommendations
  9. 9Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example

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6.4.2.1 Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags, Interrupts, and GPIOs

Table 6-31 Page 0 / Register 0 (0x00): Page Control Register

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 0000 0000: Page 0 selected
0000 0001: Page 1 selected
...
1111 1110: Page 254 selected
1111 1111: Page 255 selected

Table 6-32 Page 0 / Register 1 (0x01): Software Reset

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D1 R/W 0000 000 Reserved. Write only zeros to these bits.
D0 R/W 0 0: Don't care
1: Self-clearing software reset for control register

Table 6-33 Page 0 / Register 2 (0x02): Reserved

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R XXXX XXXX Reserved. Do not write to this register.

Table 6-34 Page 0 / Register 3 (0x03): OT FLAG

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7-D2 R XXXX XX Reserved. Do not write to these bits.
D1 R 1 0: Overtemperature protection flag (active-low). Valid only if speaker amplifier is powered up
1: Normal operation
D0 R/W X Reserved. Do not write to these bits.

Table 6-35 Page 0 / Register 4 (0x04): Clock-Gen Muxing(1)

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D4 R/W 0000 Reserved. Write only zeros to these bits.
D3–D2 R/W 00 00: PLL_CLKIN = MCLK (device pin)
01: PLL_CLKIN = BCLK (device pin)
10: PLL_CLKIN = GPIO1 (device pin)
11: PLL_CLKIN = DIN (can be used for the system where DAC is not used)
D1–D0 R/W 00 00: CODEC_CLKIN = MCLK (device pin)
01: CODEC_CLKIN = BCLK (device pin)
10: CODEC_CLKIN = GPIO1 (device pin)
11: CODEC_CLKIN = PLL_CLK (generated on-chip)
(1) See Section 6.3.11 for more details on clock generation mutiplexing and dividers.

Table 6-36 Page 0 / Register 5 (0x05): PLL P and R Values

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 0: PLL is powered down.
1: PLL is powered up.
D6–D4 R/W 001 000: PLL divider P = 8
001: PLL divider P = 1
010: PLL divider P = 2
...
110: PLL divider P = 6
111: PLL divider P = 7
D3–D0 R/W 0001 0000: PLL multiplier R = 16
0001: PLL multiplier R = 1
0010: PLL multiplier R = 2
...
1110: PLL multiplier R = 14
1111: PLL multiplier R = 15

Table 6-37 Page 0 / Register 6 (0x06): PLL J-Value

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D6 R/W 00 Reserved. Write only zeros to these bits.
D5–D0 R/W 00 0100 00 0000: Do not use (reserved)
00 0001: PLL multiplier J = 1
00 0010: PLL multiplier J = 2
...
11 1110: PLL multiplier J = 62
11 1111: PLL multiplier J = 63

Table 6-38 Page 0 / Register 7 (0x07): PLL D-Value MSB(1)

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D6 R/W 00 Reserved. Write only zeros to these bits.
D5–D0 R/W 00 0000 PLL fractional multiplier D-value MSB bits D[13:8]
(1) Note that this register is updated only when Page 0 / Register 8 is written immediately after Page 0 / Register 7.

Table 6-39 Page 0 / Register 8 (0x08): PLL D-Value LSB(1)

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 PLL fractional multiplier D-value LSB bits D[7:0]
(1) Note that Page 0 / Register 8 must be written immediately after Page 0 / Register 7.

Table 6-40 Page 0 / Register 9 (0x09) and Page 0 / Register 10 (0x0A): Reserved

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R XXXX XXXX Reserved.

Table 6-41 Page 0 / Register 11 (0x0B): DAC NDAC_VAL

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 0: DAC NDAC divider is powered down.
1: DAC NDAC divider is powered up.
D6–D0 R/W 000 0001 000 0000: DAC NDAC divider = 128
000 0001: DAC NDAC divider = 1
000 0010: DAC NDAC divider = 2
...
111 1110: DAC NDAC divider = 126
111 1111: DAC NDAC divider = 127

Table 6-42 Page 0 / Register 12 (0x0C): DAC MDAC_VAL

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 0: DAC MDAC divider is powered down.
1: DAC MDAC divider is powered up.
D6–D0 R/W 000 0001 000 0000: DAC MDAC divider = 128
000 0001: DAC MDAC divider = 1
000 0010: DAC MDAC divider = 2
...
111 1110: DAC MDAC divider = 126
111 1111: DAC MDAC divider = 127

Table 6-43 Page 0 / Register 13 (0x0D): DAC DOSR_VAL MSB

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D2 R/W 0000 00 Reserved
D1–D0 R/W 00 DAC OSR value DOSR(9:8)

Table 6-44 Page 0 / Register 14 (0x0E): DAC DOSR_VAL LSB

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1000 0000 DAC OSR Value DOSR (7:0)
0000 0000: DAC OSR (7:0) = 1024 (MSB page 0 / register 13, bits D1–D0 = 00)
0000 0001: Reserved
0000 0010: DAC OSR (7:0) = 2 (MSB page 0 / register 13, bits D1–D0 = 00)
...
1111 1110: DAC OSR (7:0) = 1022 (MSB page 0 / register 13, bits D1–D0 = 11)
1111 1111: DAC OSR (7:0) =

Table 6-45 Page 0 / Register 15 (0x0F) through Page 0 / Register 24 (0x18): Reserved

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W XXXX XXXX Reserved. Do not write to these registers.

Table 6-46 Page 0 / Register 25 (0x19): CLKOUT MUX

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D3 R/W 0000 0 Reserved
D2–D0 R/W 000 000: CDIV_CLKIN = MCLK (device pin)
001: CDIV_CLKIN = BCLK (device pin)
010: CDIV_CLKIN = DIN (can be used for the systems where DAC is not required)
011: CDIV_CLKIN = PLL_CLK (generated on-chip)
100: CDIV_CLKIN = DAC_CLK (DAC DSP clock - generated on-chip)
101: CDIV_CLKIN = DAC_MOD_CLK (generated on-chip)
110: Reserved
111: Reserved

Table 6-47 Page 0 / Register 26 (0x1A): CLKOUT M_VAL

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 0: CLKOUT M divider is powered down.
1: CLKOUT M divider is powered up.
D6–D0 R/W 000 0001 000 0000: CLKOUT divider M = 128
000 0001: CLKOUT divider M = 1
000 0010: CLKOUT divider M = 2
...
111 1110: CLKOUT divider M = 126
111 1111: CLKOUT divider M = 127

Table 6-48 Page 0 / Register 27 (0x1B): Codec Interface Control 1

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D6 R/W 00 00: Codec interface = I2S
01: Codec Interface = DSP
10: Codec interface = RJF
11: Codec interface = LJF
D5–D4 R/W 00 00: Codec interface word length = 16 bits
01: Codec interface word length = 20 bits
10: Codec interface word length = 24 bits
11: Codec interface word length = 32 bits
D3 R/W 0 0: BCLK is input
1: BCLK is output
D2 R/W 0 0: WCLK is input
1: WCLK is output
D1–D0 R/W 0 Reserved

Table 6-49 Page 0 / Register 28 (0x1C): Data-Slot Offset Programmability

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 Offset (Measured With Respect to WCLK Rising Edge in DSP Mode)
0000 0000: Offset = 0 BCLKs
0000 0001: Offset = 1 BCLK
0000 0010: Offset = 2 BCLKs
...
1111 1110: Offset = 254 BCLKs
1111 1111: Offset = 255 BCLKs

Table 6-50 Page 0 / Register 29 (0x1D): Codec Interface Control 2

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D4 R/W 0000 Reserved
D3 R/W 0 0: BCLK is not inverted (valid for both primary and secondary BCLK)
1: BCLK is inverted (valid for both primary and secondary BCLK)
D2 R/W 0 BCLK and WCLK Active Even With Codec Powered Down (Valid for Both Primary and Secondary BCLK)
0: Disabled
1: Enabled
D1–D0 R/W 00 00: BDIV_CLKIN = DAC_CLK (generated on-chip)
01: BDIV_CLKIN = DAC_MOD_CLK (generated on-chip)
10: Reserved
11: Reserved

Table 6-51 Page 0 / Register 30 (0x1E): BCLK N_VAL

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 0: BCLK N-divider is powered down.
1: BCLK N-divider is powered up.
D6–D0 R/W 000 0001 000 0000: BCLK divider N = 128
000 0001: BCLK divider N = 1
000 0010: BCLK divider N = 2
...
111 1110: BCLK divider N = 126
111 1111: BCLK divider N = 127

Table 6-52 Page 0 / Register 31 (0x1F): Codec Secondary Interface Control 1

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D5 R/W 000 000: Secondary BCLK is obtained from GPIO1 pin.
001: Secondary BCLK is not obtained from the GPIO1 pin.
010: Reserved.
011: Reserved.
100: Reserved
101: Reserved.
110: Reserved.
111: Reserved
D4–D2 R/W 000 000: Secondary WCLK is obtained from GPIO1 pin.
001: Secondary WCLK is not obtained from the GPIO1 pin.
010: Reserved.
011: Reserved.
100: Reserved
101: Reserved.
110: Reserved.
111: Reserved
D1–D0 R/W 00 00: Secondary DIN is obtained from the GPIO1 pin.
01: Secondary DIN is not obtained from the GPIO1 pin.
10: Reserved.
10–11: Reserved

Table 6-53 Page 0 / Register 32 (0x20): Codec Secondary Interface Control 2

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D4 R/W 0000 Reserved
D3 R/W 0 0: Primary BCLK is fed to codec serial-interface and ClockGen blocks.
1: Secondary BCLK is fed to codec serial-interface and ClockGen blocks.
D2 R/W 0 0: Primary WCLK is fed to codec serial-interface block.
1: Secondary WCLK is fed to codec serial-interface block.
D1 R/W 0 Reserved.
D0 R/W 0 0: Primary DIN is fed to codec serial-interface block.
1: Secondary DIN is fed to codec serial-interface block.

Table 6-54 Page 0 / Register 33 (0x21): Codec Secondary Interface Control 3

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 0: Primary BCLK output = internally generated BCLK clock
1: Primary BCLK output = secondary BCLK
D6 R/W 0 0: Secondary BCLK output = primary BCLK
1: Secondary BCLK output = internally generated BCLK clock
D5–D4 R/W 00 00: Primary WCLK output = internally generated DAC_fS
01: Reserved
10: Primary WCLK output = secondary WCLK
11: Reserved
D3–D2 R/W 00 00: Secondary WCLK output = primary WCLK
01: Secondary WCLK output = internally generated DAC_fS clock
10: Reserved
11: Reserved
D1–D0 R/W 0 Reserved

Table 6-55 Page 0 / Register 34 (0x22): I2C Bus Condition

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D6 R/W 00 Reserved. Write only the reset value to these bits.
D5 R/W 0 0: I2C general-call address is ignored.
1: Device accepts I2C general-call address.
D4–D0 R/W 0 0000 Reserved. Write only zeros to these bits.

Table 6-56 Page 0 / Register 35 (0x23) and Page 0 / Register 36 (0x24): Reserved

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W XXXX XXXX Reserved. Write only zeros to these bits.

Table 6-57 Page 0 / Register 37 (0x25): DAC Flag Register

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R 0 0: Left-channel DAC powered down
1: Left-channel DAC powered up
D6 R/W X Reserved. Write only zero to this bit.
D5 R 0 0: HPL driver powered down
1: HPL driver powered up
D4 R 0 0: Left-channel class-D driver powered down
1: Left-channel class-D driver powered up
D3 R 0 0: Right-channel DAC powered down
1: Right-channel DAC powered up
D2 R/W X Reserved. Write only zero to this bit.
D1 R 0 0: HPR driver powered down
1: HPR driver powered up
D0 R 0 0: Right-channel class-D driver powered down
1: Right-channel class-D driver powered up

Table 6-58 Page 0 / Register 38 (0x26): DAC Flag Register

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D5 R/W XXX Reserved. Do not write to these bits.
D4 R 0 0: Left-channel DAC PGA applied gain ≠ programmed gain
1: Left-channel DAC PGA applied gain = programmed gain
D3–D1 R/W XXX Reserved. Write only zeros to these bits.
D0 R 0 0: Right-channel DAC PGA applied gain ≠ programmed gain
1: Right-channel DAC PGA applied gain = programmed gain

Table 6-59 Page 0 / Register 39 (0x27): Overflow Flags

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7(1) R 0 Left-Channel DAC Overflow Flag
0: Overflow has not occurred.
1: Overflow has occurred.
D6(1) R 0 Right-Channel DAC Overflow Flag
0: Overflow has not occurred.
1: Overflow has occurred.
D5(1) R 0 DAC Barrel Shifter Output Overflow Flag
0: Overflow has not occurred.
1: Overflow has occurred.
D4–D0 R 0 Reserved.
(1) Sticky flag bIt. These is a read-only bit. This bit is automatically cleared once it is read and is set only if the source trigger occurs again.

Table 6-60 Page 0 / Register 40 (0x28) Through Page 0 / Register 43 (0x2B): Reserved

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W XXXX XXXX Reserved. Write only the reset value to these bits.

Table 6-61 Page 0 / Register 44 (0x2C): DAC Interrupt Flags (Sticky Bits)

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7(1) R 0 0: No short circuit is detected at HPL / left class-D driver.
1: Short circuit is detected at HPL / left class-D driver.
D6(1) R 0 0: No short circuit is detected at HPR / right class-D driver.
1: Short circuit is detected at HPR / right class-D driver.
D5(1) R X 0: No headset button pressed.
1: Headset button pressed.
D4(1) R X 0: No headset insertion or removal is detected.
1: Headset insertion or removal is detected.
D3(1) R 0 0: Left DAC signal power is less than or equal to the signal threshold of DRC.
1: Left DAC signal power is above the signal threshold of DRC.
D2(1) R 0 0: Right DAC signal power is less than or equal to the signal threshold of DRC.
1: Right DAC signal power is above the signal threshold of DRC.
D1-D0 R 0 Reserved.

Table 6-62 Page 0 / Register 45 (0x2D): Reserved

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W XXXX XXXX Reserved. Write only zeros to these bits.

Table 6-63 Page 0 / Register 46 (0x2E): Interrupt Flags—DAC

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R 0 0: No short circuit detected at HPL / left class-D driver.
1: Short circuit detected at HPL / left class-D driver.
D6 R 0 0: No short circuit detected at HPR / right class-D driver
1: Short circuit detected at HPR / right class-D driver
D5 R X 0: No headset button pressed.
1: Headset button pressed.
D4 R X 0: Headset removal detected.
1: Headset insertion detected.
D3 R 0 0: Left DAC signal power is less than or equal to signal threshold of DRC.
1: Left DAC signal power is greater than signal threshold of DRC.
D2 R 0 0: Right DAC signal power is less than or equal to signal threshold of DRC.
1: Right DAC signal power is greater than signal threshold of DRC.
D1–D0 R 00 Reserved.

Table 6-64 Page 0 / Register 47 (0x2F): Reserved

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R 0000 0000 Reserved.

Table 6-65 Page 0 / Register 48 (0x30): INT1 Control Register

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 0: Headset-insertion detect interrupt is not used in the generation of INT1 interrupt.
1: Headset-insertion detect interrupt is used in the generation of INT1 interrupt.
D6 R/W 0 0: Button-press detect interrupt is not used in the generation of INT1 interrupt.
1: Button-press detect interrupt is used in the generation of INT1 interrupt.
D5 R/W 0 0: DAC DRC signal-power interrupt is not used in the generation of INT1 interrupt.
1: DAC DRC signal-power interrupt is used in the generation of INT1 interrupt.
D4 R/W 0 Reserved
D3 R/W 0 0: Short-circuit interrupt is not used in the generation of INT1 interrupt.
1: Short-circuit interrupt is used in the generation of INT1 interrupt.
D2 R/W 0 0: DAC data overflow does not result in an INT1 interrupt.
1: DAC data overflow results in an INT1 interrupt.
D1 R/W 0 Reserved
D0 R/W 0 0: INT1 is only one pulse (active-high) of typical 2-ms duration.
1: INT1 is multiple pulses (active-high) of typical 2-ms duration and 4-ms period, until flag register 44 is read by the user.

Table 6-66 Page 0 / Register 49 (0x31): INT2 Control Register

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 0: Headset-insertion detect interrupt is not used in the generation of INT2 interrupt.
1: Headset-insertion detect interrupt is used in the generation of INT2 interrupt.
D6 R/W 0 0: Button-press detect interrupt is not used in the generation of INT2 interrupt.
1: Button-press detect interrupt is used in the generation of INT2 interrupt.
D5 R/W 0 0: DAC DRC signal-power interrupt is not used in the generation of INT2 interrupt.
1: DAC DRC signal-power interrupt is used in the generation of INT2 interrupt.
D4 R/W 0 Reserved
D3 R/W 0 0: Short-circuit interrupt is not used in the generation of INT2 interrupt.
1: Short-circuit interrupt is used in the generation of INT2 interrupt.
D2 R/W 0 0: DAC data overflow does not result in an INT2 interrupt.
1: DAC data overflow results in an INT2 interrupt.
D1 R/W 0 Reserved
D0 R/W 0 0: INT2 is only one pulse (active-high) of typical 2-ms duration.
1: INT2 is multiple pulses (active-high) of typical 2-ms duration and 4-ms period, until flag register 44is read by the user.

Table 6-67 Page 0 / Register 50 (0x32): Reserved

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7-D0 R/W 0000 0000 Reserved. Write only reset values.

Table 6-68 Page 0 / Register 52 (0x34): Reserved

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W XXXX XXXX Reserved. Do not write any value other than reset value.

Table 6-69 Page 0 / Register 53: Reserved

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R 0000 0000 Reserved

Table 6-70 Page 0 / Register 54 (0x36): DIN (IN Pin) Control

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D3 R/W 0000 0 Reserved
D2–D1 R/W 01 00: DIN disabled (input buffer powered down)
01: DIN enabled (can be used as DIN for codec interface or into ClockGen block)
10: DIN is used as general-purpose input (GPI)
11: Reserved
D0 R X DIN input-buffer value

Table 6-71 Page 0 / Register 55 (0x37) through Page 0 / Register 59 (0x3B): Reserved

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R XXXX XXXX Reserved. Do not write to these registers.

Table 6-72 Page 0 / Register 60 (0x3C): DAC Processing Block Selection

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D5 R/W 000 Reserved. Write only default value.
D4–D0 R/W 00 0001 0 0000: Reserved. Do not use.
0 0001: DAC signal-processing block PRB_P1
0 0010: DAC signal-processing block PRB_P2
0 0011: DAC signal-processing block PRB_P3
0 0100: DAC signal-processing block PRB_P4
...
1 1000: DAC signal-processing block PRB_P24
1 1001: DAC signal-processing block PRB_P25
1 1010–1 1111: Reserved. Do not use.

Table 6-73 Page 0 / Register 61 (0x3D)Through Page 0 / Register 62: Reserved

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R XXXX XXXX Reserved. Do not write.

Table 6-74 Page 0 / Register 63 (0x3F): DAC Data-Path Setup

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 0: Left-channel DAC is powered down.
1: Left-channel DAC is powered up.
D6 R/W 0 0: Right-channel DAC is powered down.
1: Right-channel DAC is powered up.
D5–D4 R/W 01 00: Left-channel DAC data path = off
01: Left-channel DAC data path = left data
10: Left-channel DAC data path = right data
11: Left-channel DAC data path = left-channel and right-channel data [(L + R) / 2]
D3–D2 R/W 01 00: Right-channel DAC data path = off
01: Right-channel DAC data path = right data
10: Right-channel DAC data path = left data
11: Right-channel DAC data path = left-channel and right-channel data [(L + R) / 2]
D1–D0 R/W 00 00: DAC-channel volume-control soft-stepping is enabled for one step per sample period.
01: DAC-channel volume-control soft-stepping is enabled for one step per two sample periods.
10: DAC-channel volume-control soft-stepping is disabled.
11: Reserved. Do not write this sequence to these bits.

Table 6-75 Page 0 / Register 64 (0x40): DAC Volume Control

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D4 R/W 0000 Reserved. Write only zeros to these bits.
D3 R/W 1 0: Left-channel DAC not muted
1: Left-channel DAC muted
D2 R/W 1 0: Right-channel DAC not muted
1: Right-channel DAC muted
D1–D0 R/W 00 00: Left and right channels have independent volume control.(1)
01: Left-channel volume control Is the programmed value of right-channel volume control.
10: Right-channel volume control is the programmed value of left-channel volume control.
11: Same as 00
(1) When DRC is enabled, left and right channel volume controls are always independent. Program bits D1–D0 to 00.

Table 6-76 Page 0 / Register 65 (0x41): DAC Left Volume Control

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 Left DAC Channel Digital Volume Control Setting
0111 1111–0011 0001: Reserved. Do not use
0011 0000: Digital volume control = 24 dB
0010 1111: Digital volume control = 23.5 dB
0010 1110: Digital volume control = 23 dB
...

0000 0001: Digital volume control = 0.5 dB
0000 0000: Digital volume control = 0 dB
1111 1111: Digital volume control = –0.5 dB
...
1000 0010: Digital volume control = –63 dB
1000 0001: Digital volume control = –63.5 dB
1000 0000: Reserved.

Table 6-77 Page 0 / Register 66 (0x42): DAC Right Volume Control

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 Right DAC Channel Digital Volume Control Setting
0111 1111–0011 0001: Reserved. Do not use
0011 0000: Digital volume control = 24 dB
0010 1111: Digital volume control = 23.5 dB
0010 1110: Digital volume control = 23 dB
...

0000 0001: Digital volume control = 0.5 dB
0000 0000: Digital volume control = 0 dB
1111 1111: Digital volume control = –0.5 dB
...
1000 0010: = –63 dB
1000 0001: = –63.5 dB
1000 0000: Reserved.

Table 6-78 Page 0 / Register 67 (0x43): Headset Detection

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 0: Headset detection disabled
1: Headset detection enabled
D6–D5 R XX 00: No headset detected
01: Headset without microphone is detected
10: Reserved
11: Headset with microphone is detected
D4–D2 R/W 000 Debounce Programming for Glitch Rejection During Headset Detection(1)
000: 16 ms (sampled with 2-ms clock)
001: 32 ms (sampled with 4-ms clock)
010: 64 ms (sampled with 8-ms clock)
011: 128 ms (sampled with 16-ms clock)
100: 256 ms (sampled with 32-ms clock)
101: 512 ms (sampled with 64-ms clock)
110: Reserved
111: Reserved
D1–D0 R/W 00 Debounce programming for glitch rejection during headset button-press detection
00: 0 ms
01: 8 ms (sampled with 1-ms clock)
10: 16 ms (sampled with 2-ms clock)
11: 32 ms (sampled with 4-ms clock)
(1) Note that these times are generated using the 1 MHz reference clock which is defined in Page 3 / Register 16.

Table 6-79 Page 0 / Register 68 (0x44): DRC Control 1

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 Reserved. Write only the reset value to these bits.
D6 R/W 0 0: DRC disabled for left channel
1: DRC enabled for left channel
D5 R/W 0 0: DRC disabled for right channel
1: DRC enabled for right channel
D4–D2 R/W 011 000: DRC threshold = –3 dB
001: DRC threshold = –6 dB
010: DRC threshold = –9 dB
011: DRC threshold = –12 dB
100: DRC threshold = –15 dB
101: DRC threshold = –18 dB
110: DRC threshold = –21 dB
111: DRC threshold = –24 dB
D1–D0 R/W 11 00: DRC hysteresis = 0 dB
01: DRC hysteresis = 1 dB
10: DRC hysteresis = 2 dB
11: DRC hysteresis = 3 dB

Table 6-80 Page 0 / Register 69 (0x45): DRC Control 2

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D R 0 Reserved. Write only the reset value to these bits.
D6–D3 R/W 0111 DRC Hold Time
0000: DRC Hold Disabled
0001: DRC Hold Time = 32 DAC Word Clocks
0010: DRC Hold Time = 64 DAC Word Clocks
0011: DRC Hold Time = 128 DAC Word Clocks
0100: DRC Hold Time = 256 DAC Word Clocks
0101: DRC Hold Time = 512 DAC Word Clocks
0110: DRC Hold Time = 1024 DAC Word Clocks
0111: DRC Hold Time = 2048 DAC Word Clocks
1000: DRC Hold Time = 4096 DAC Word Clocks
1001: DRC Hold Time = 8192 DAC Word Clocks
1010: DRC Hold Time = 16 384 DAC Word Clocks
1011: DRC Hold Time = 32 768 DAC Word Clocks
1100: DRC Hold Time = 65 536 DAC Word Clocks
1101: DRC Hold Time = 98 304 DAC Word Clocks
1110: DRC Hold Time = 131 072 DAC Word Clocks
1111: DRC Hold Time = 163 840 DAC Word Clocks
D2-D0 R 000 Reserved. Write only the reset value to these bits.

Table 6-81 Page 0 / Register 70 (0x46): DRC Control 3

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D4 R/W 0000 0000: DRC attack rate = 4 dB per DAC Word Clock
0001: DRC attack rate = 2 dB per DAC word clock
0010: DRC attack rate = 1 dB per DAC word clock
...
1110: DRC attack rate = 2.4414e–5 dB per DAC word clock
1111: DRC attack rate = 1.2207e–5 dB per DAC word clock
D3–D0 R/W 0000 Decay Rate is defined as DR / 2[bits D3-D0 value] dB per DAC Word Clock, where DR = 0.015625 dB
0000: DRC decay rate (DR) = 0.015625 dB per DAC Word Clock
0001: DRC decay rate = DR / 2 dB per DAC Word Clock
0010: DRC decay rate = DR / 22 dB per DAC Word Clock
0011: DRC decay rate = DR / 23 dB per DAC Word Clock
0100: DRC decay rate = DR / 24 dB per DAC Word Clock
0101: DRC decay rate = DR / 25 dB per DAC Word Clock
0110: DRC decay rate = DR / 26 dB per DAC Word Clock
0111: DRC decay rate = DR / 27 dB per DAC Word Clock
1000: DRC decay rate = DR / 28 dB per DAC Word Clock
1001: DRC decay rate = DR / 29 dB per DAC Word Clock
1010: DRC decay rate = DR / 210 dB per DAC Word Clock
1011: DRC decay rate = DR / 211 dB per DAC Word Clock
1100: DRC decay rate = DR / 212 dB per DAC Word Clock
1101: DRC decay rate = DR / 213 dB per DAC Word Clock
1110: DRC decay rate = DR / 214 dB per DAC Word Clock
1111: DRC decay rate = DR / 215 dB per DAC Word Clock

Table 6-82 Page 0 / Register 71 (0x47): Left Beep Generator (1)

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 0: Beep generator is disabled.
1: Beep generator is enabled (self-clearing based on beep duration).
D6 R/W 0 Reserved. Write only reset value.
D5–D0 R/W 00 0000 00 0000: Left-channel beep volume control = 2 dB
00 0001: Left-channel beep volume control = 1 dB
00 0010: Left-channel beep volume control = 0 dB
00 0011: Left-channel beep volume control = –1 dB
...
11 1110: Left-channel beep volume control = –60 dB
11 1111: Left-channel beep volume control = –61 dB
(1) The beep generator is only available in PRB_P25 DAC processing mode.

Table 6-83 Page 0 / Register 72 (0x48): Right Beep Generator

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D6 R/W 00 00: Left and right channels have independent beep volume control.
01: Left-channel beep volume control is the programmed value of right-channel beep volume control.
10: Right-channel beep volume control is the programmed value of left-channel beep volume control.
11: Same as 00
D5–D0 R/W 00 0000 00 0000: Right-channel beep volume control = 2 dB
00 0001: Right-channel beep volume control = 1 dB
00 0010: Right-channel beep volume control = 0 dB
00 0011: Right-channel beep volume control = –1 dB
...
11 1110: Right-channel beep volume control = –60 dB
11 1111: Right-channel beep volume control = –61 dB

Table 6-84 Page 0 / Register 73 (0x49): Beep Length MSB

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 8 MSBs out of 24 bits for the number of samples for which the beep must be generated.

Table 6-85 Page 0 / Register 74 (0x4A): Beep-Length Middle Bits

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 8 middle bits out of 24 bits for the number of samples for which the beep must be generated.

Table 6-86 Page 0 / Register 75 (0x4B): Beep Length LSB

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1110 1110 8 LSBs out of 24 bits for the number of samples for which beep must be generated.

Table 6-87 Page 0 / Register 76 (0x4C): Beep Sin(x) MSB

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0001 0000 8 MSBs out of 16 bits for sin(2π × fin / fS), where fin is the beep frequency and fS is the DAC sample rate.

Table 6-88 Page 0 / Register 77 (0x4D): Beep Sin(x) LSB

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1101 1000 8 LSBs out of 16 bits for sin(2π × fin / fS), where fin is the beep frequency and fS is the DAC sample rate.

Table 6-89 Page 0 / Register 78 (0x4E): Beep Cos(x) MSB

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0111 1110 8 MSBs out of 16 bits for cos(2π × fin / fS), where fin is the beep frequency and fS is the DAC sample rate.

Table 6-90 Page 0 / Register 79 (0x4F): Beep Cos(x) LSB

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1110 0011 8 LSBs out of 16 bits for cos(2π × fin / fS), where fin is the beep frequency and fS is the DAC sample rate.

Table 6-91 Page 0 / Register 80 (0x50) Through Page 0 / Register 115 (0x73): Reserved

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W XXXX XXXX Reserved. Do not write to these registers.

Table 6-92 Page 0 / Register 116 (0x74): VOL/MICDET-Pin SAR ADC — Volume Control

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 0: DAC volume control is controlled by control register. (7-bit Vol ADC is powered down)
1: DAC volume control is controlled by pin.
D6 R/W 0 0: Internal on-chip RC oscillator is used for the 7-bit Vol ADC for pin volume control.
1: MCLK is used for the 7-bit Vol ADC for pin volume control.
D5–D4 R/W 00 00: No hysteresis for volume control ADC output
01: Hysteresis of ±1 bit
10: Hysteresis of ±2 bits
11: Reserved. Do not write this sequence to these bits.
D3 R/W 0 Reserved. Write only reset value.
D2–D0 R/W 000 Throughput of the 7-bit Vol ADC for pin volume control, frequency based on  MCLK or internal oscillator.
MCLK = 12 MHz Internal Oscillator Source
000: Throughput =
001: Throughput =
010: Throughput =
011: Throughput =
100: Throughput =
101: Throughput =
110: Throughput =
111: Throughput =		 15.625 Hz
31.25 Hz
62.5 Hz
125 Hz
250 Hz
500 Hz
1 kHz
2 kHz		 10.68 Hz
21.35 Hz
42.71 Hz
8.2 Hz
170 Hz
340 Hz
680 Hz
1.37 kHz
Note: These values are based on a nominal oscillator frequency of 8.2 MHz. The values scale to the actual oscillator frequency.

Table 6-93 Page 0 / Register 117 (0x75): VOL/MICDET-Pin Gain

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 Reserved. Write only zero to this bit.
D6–D0 R XXX XXXX 000 0000: Gain applied by pin volume control = 18 dB
000 0001: Gain applied by pin volume control = 17.5 dB
000 0010: Gain applied by pin volume control = 17 dB
...
010 0011: Gain applied by pin volume control = 0.5 dB
010 0100: Gain applied by pin volume control = 0 dB
010 0101: Gain applied by pin volume control = –0.5 dB
...
101 1001: Gain applied by pin volume control = –26.5 dB
101 1010: Gain applied by pin volume control = –27 dB
101 1011: Gain applied by pin volume control = –28 dB
...
111 1101: Gain applied by pin volume control = –62 dB
111 1110: Gain applied by pin volume control = –63 dB
111 1111: Reserved.

Table 6-94 Page 0 / Register 118 (0x76) Through Page 0 / Register 127 (0x7F): Reserved

BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W XXXX XXXX Reserved. Do not write to these registers.