ZHCSOF3G April   2006  – July 2021 TLV320AIC3106

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements: Audio Data Serial Interface (1)
    7. 8.7 Timing Diagrams
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Hardware Reset
      2. 10.3.2  Digital Audio Data Serial Interface
        1. 10.3.2.1 Right-Justified Mode
        2. 10.3.2.2 Left-Justified Mode
        3. 10.3.2.3 I2S Mode
        4. 10.3.2.4 DSP Mode
        5. 10.3.2.5 TDM Data Transfer
      3. 10.3.3  Audio Data Converters
        1. 10.3.3.1 Audio Clock Generation
        2. 10.3.3.2 Stereo Audio ADC
          1. 10.3.3.2.1 Stereo Audio ADC High-Pass Filter
          2. 10.3.3.2.2 Automatic Gain Control (AGC)
            1. 10.3.3.2.2.1 Target Level
            2. 10.3.3.2.2.2 Attack Time
            3. 10.3.3.2.2.3 Decay Time
            4. 10.3.3.2.2.4 Noise Gate Threshold
            5. 10.3.3.2.2.5 Maximum PGA Gain Applicable
        3. 10.3.3.3 Stereo Audio DAC
          1. 10.3.3.3.1 Digital Audio Processing for Playback
          2. 10.3.3.3.2 Digital Interpolation Filter
          3. 10.3.3.3.3 Delta-Sigma Audio DAC
          4. 10.3.3.3.4 Audio DAC Digital Volume Control
          5. 10.3.3.3.5 Increasing DAC Dynamic Range
          6. 10.3.3.3.6 Analog Output Common-Mode Adjustment
          7. 10.3.3.3.7 Audio DAC Power Control
      4. 10.3.4  Audio Analog Inputs
      5. 10.3.5  Analog Fully Differential Line Output Drivers
      6. 10.3.6  Analog High Power Output Drivers
      7. 10.3.7  Input Impedance and VCM Control
      8. 10.3.8  General-Purpose I/O
      9. 10.3.9  Digital Microphone Connectivity
      10. 10.3.10 Micbias Generation
      11. 10.3.11 Short Circuit Output Protection
      12. 10.3.12 Jack/Headset Detection
    4. 10.4 Device Functional Modes
      1. 10.4.1 Bypass Path Mode
        1. 10.4.1.1 Analog Input Bypass Path Functionality
        2. 10.4.1.2 ADC PGA Signal Bypass Path Functionality
        3. 10.4.1.3 Passive Analog Bypass During Powerdown
      2. 10.4.2 Digital Audio Processing for Record Path
    5. 10.5 Programming
      1. 10.5.1 Digital Control Serial Interface
        1. 10.5.1.1 SPI Control Mode
          1. 10.5.1.1.1 SPI Communication Protocol
          2. 10.5.1.1.2 Limitation on Register Writing
          3. 10.5.1.1.3 Continuous Read / Write Operation
        2. 10.5.1.2 I2C Control Interface
          1. 10.5.1.2.1 I2C BUS Debug in a Glitched System
    6. 10.6 Register Maps
      1. 10.6.1 Output Stage Volume Controls
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Examples
  14. 14Device and Documentation Support
    1. 14.1 接收文档更新通知
    2. 14.2 支持资源
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 术语表

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RGZ|48
  • ZXH|80
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Pin Configuration and Functions

GUID-5F3B0092-A3D8-4F55-BD04-5C5F9AA7F5C8-low.gif
Solder the VQFN thermal pad to the ground plane (DRVSS).
Figure 7-1 RGZ Package,48-Pin VQFN,Bottom View
GUID-02C1D38E-4CEF-4610-94E9-A2FE9B59DC2F-low.gif
The shaded balls are not connected to the die, but are electrically connected to each other. Is recommended to solder them to analog ground in order to enhance the thermal performance of the device.
Figure 7-2 ZQE Package,80-Ball BGA Microstar Junior,Bottom View
Table 7-1 Pin Functions
PIN I/O DESCRIPTION
NAME VQFN BGA BALL
MICBIAS 13 A2 O Microphone bias voltage output
MIC3R 14 A1 I MIC3 input (right or multifunction)
AVSS_ADC 15 C2,D2 – Analog ADC ground supply, 0 V
DRVDD 16,17 B1,C1 – ADC analog and output driver voltage supply, 2.7 V–3.6 V
HPLOUT 18 D1 O High-power output driver (left +)
HPLCOM 19 E1 O High-power output driver (left – or multifunctional)
DRVSS 20,21 E2,F2 – Analog output driver ground supply, 0 V
HPRCOM 22 F1 O High-power output driver (right – or multifunctional)
HPROUT 23 G1 O High-power output driver (right +)
DRVDD 24 H1 – ADC analog and output driver voltage supply, 2.7 V–3.6 V
AVDD_DAC 25 J1 – Analog DAC voltage supply, 2.7 V–3.6 V
AVSS_DAC 26 G2,H2 – Analog DAC ground supply, 0 V
MONO_LOP 27 J2 O Mono line output (+)
MONO_LOM 28 J3 O Mono line output (–)
LEFT_LOP 29 J4 O Left line output (+)
LEFT_LOM 30 J5 O Left line output (–)
RIGHT_LOP 31 J6 O Right line output (+)
RIGHT_LOM 32 J7 O Right line output (–)
RESET 33 H8 I Reset
GPIO2 34 J8 I/O General-purpose input/output #2 (input/output)/digital microphone data input/PLL clock input/audio serial data bus bit clock input/output
GPIO1 35 J9 I/O General-purpose input/output #1 (input/output)/PLL/clock mux output/short circuit interrupt/AGC noise flag/digital microphone clock audio serial data bus word clock input/output
DVDD 36 H9 – Digital core voltage supply, 1.65 V–1.95 V
MCLK 37 G8 I Master clock input
BCLK 38 G9 I Audio serial data bus bit clock (input/output)
WCLK 39 F9 I Audio serial data bus word clock (input/output)
DIN 40 E9 I Audio serial data bus data input (input)
DOUT 41 F8 O Audio serial data bus data output (output)
DVSS 42 D9 – Digital core / I/O ground supply, 0V
SELECT 43 E8 I Control mode select pin (1 = SPI, 0 = I2C)
IOVDD 44 C9 – I/O voltage supply, 1.1 V–3.6 V
MFP0 45 B8 I Multifunction pin #0 – SPI chip select / GPI / I2C address pin #0
MFP1 46 B9 I Multifunction pin #1 – SPI serial clock / GPI / I2C address pin #1S
MFP2 47 A8 I Multifunction pin #2 – SPI MISO slave serial data output / GPOI
MFP3 48 A9 I Multifunction pin #3 – SPI MOSI slave serial data input/GPI/audio serial data bus data input
SCL 1 C8 I/O I2C serial clock/GPIO
SDA 2 D8 I/O I2C serial data input/output/GPIO
NC – A7 – Not connected
LINE1LP 3 A6 I MIC1 or Line1 analog input (left + or multifunction)
LINE1LM 4 A5 I MIC1 or Line1 analog input (left – or multifunction)
LINE1RP 5 B7 I MIC1 or Line1 analog input (right + or multifunction)
LINE1RM 6 B6 I MIC1 or Line1 analog input (right – or multifunction)
LINE2LP 7 A4 I MIC2 or Line2 analog input (left + or multifunction)
LINE2LM 8 B5 I MIC2 or Line2 analog input (left – or multifunction)
LINE2RP 9 B4 I MIC2 or Line2 analog input (right + or multifunction)
LINE2RM 10 A3 I MIC2 or Line2 analog input (right – or multifunction)
MIC3L 11 B3 I MIC3 input (left or multifunction)
MICDET 12 B2 I Microphone detect
NC – C4-C7,
D3-D7,
E3-E7,
F3-F7,
G3-G7,
H3-H7		 – Not connected