ZHCSFY4 December   2016 TAS5780M

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. 6.1 Internal Pin Configurations
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Power Dissipation Characteristics
    7. 7.7  MCLK Timing
    8. 7.8  Serial Audio Port Timing - Slave Mode
    9. 7.9  Serial Audio Port Timing - Master Mode
    10. 7.10 I2C Bus Timing - Standard
    11. 7.11 I2C Bus Timing - Fast
    12. 7.12 SPK_MUTE Timing
    13. 7.13 Typical Characteristics
      1. 7.13.1 Bridge Tied Load (BTL) Configuration Curves
      2. 7.13.2 Parallel Bridge Tied Load (PBTL) Configuration
  8. 8 Parametric Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-on-Reset (POR) Function
      2. 9.3.2 Device Clocking
      3. 9.3.3 Serial Audio Port
        1. 9.3.3.1 Clock Master Mode from Audio Rate Master Clock
        2. 9.3.3.2 Clock Master from a Non-Audio Rate Master Clock
        3. 9.3.3.3 Clock Slave Mode with 4-Wire Operation (SCLK, MCLK, LRCK/FS, SDIN)
        4. 9.3.3.4 Clock Slave Mode with SCLK PLL to Generate Internal Clocks (3-Wire PCM)
          1. 9.3.3.4.1 Clock Generation using the PLL
          2. 9.3.3.4.2 PLL Calculation
            1. 9.3.3.4.2.1 Examples:
        5. 9.3.3.5 Serial Audio Port - Data Formats and Bit Depths
          1. 9.3.3.5.1 Data Formats and Master/Slave Modes of Operation
        6. 9.3.3.6 Input Signal Sensing (Power-Save Mode)
      4. 9.3.4 Enable Device
        1. 9.3.4.1 Example
      5. 9.3.5 Volume Control
        1. 9.3.5.1 DAC Digital Gain Control
          1. 9.3.5.1.1 Emergency Volume Ramp Down
      6. 9.3.6 Adjustable Amplifier Gain and Switching Frequency Selection
      7. 9.3.7 Error Handling and Protection Suite
        1. 9.3.7.1 Device Overtemperature Protection
        2. 9.3.7.2 SPK_OUTxx Overcurrent Protection
        3. 9.3.7.3 Internal VAVDD Undervoltage-Error Protection
        4. 9.3.7.4 Internal VPVDD Undervoltage-Error Protection
        5. 9.3.7.5 Internal VPVDD Overvoltage-Error Protection
        6. 9.3.7.6 External Undervoltage-Error Protection
        7. 9.3.7.7 Internal Clock Error Notification (CLKE)
      8. 9.3.8 GPIO Port and Hardware Control Pins
      9. 9.3.9 I2C Communication Port
        1. 9.3.9.1 Slave Address
        2. 9.3.9.2 Register Address Auto-Increment Mode
        3. 9.3.9.3 Packet Protocol
        4. 9.3.9.4 Write Register
        5. 9.3.9.5 Read Register
        6. 9.3.9.6 DSP Book, Page, and Register Update
          1. 9.3.9.6.1 Book and Page Change
          2. 9.3.9.6.2 Swap Flag
          3. 9.3.9.6.3 Example Use
    4. 9.4 Device Functional Modes
      1. 9.4.1 Serial Audio Port Operating Modes
      2. 9.4.2 Communication Port Operating Modes
      3. 9.4.3 Speaker Amplifier Operating Modes
        1. 9.4.3.1 Stereo Mode
        2. 9.4.3.2 Mono Mode
        3. 9.4.3.3 Master and Slave Mode Clocking for Digital Serial Audio Port
    5. 9.5 Programming
      1. 9.5.1 Audio Processing Features
      2. 9.5.2 Processing Block Description
        1. 9.5.2.1  Input Scale and Mixer
          1. 9.5.2.1.1 Example
        2. 9.5.2.2  Sample Rate Converter
        3. 9.5.2.3  Parametric Equalizers (PEQ)
        4. 9.5.2.4  BQ Gain Scale
        5. 9.5.2.5  Dynamic Parametric Equalizer (DPEQ)
        6. 9.5.2.6  Two-Band Dynamic Range Control
        7. 9.5.2.7  Automatic Gain Limiter
          1. 9.5.2.7.1 Softening Filter Alpha (AEA)
          2. 9.5.2.7.2 Softening Filter Omega (AEO)
          3. 9.5.2.7.3 Attack Rate
          4. 9.5.2.7.4 Release Rate
          5. 9.5.2.7.5 Attack Threshold
        8. 9.5.2.8  Fine Volume
        9. 9.5.2.9  THD Boost
        10. 9.5.2.10 Level Meter
      3. 9.5.3 Other Processing Block Features
        1. 9.5.3.1 Number Format
          1. 9.5.3.1.1 Coefficient Format Conversion
      4. 9.5.4 Checksum
        1. 9.5.4.1 Cyclic Redundancy Check (CRC) Checksum
        2. 9.5.4.2 Exclusive or (XOR) Checksum
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 External Component Selection Criteria
      2. 10.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
      3. 10.1.3 Amplifier Output Filtering
      4. 10.1.4 Programming the TAS5780M
        1. 10.1.4.1 Resetting the TAS5780M Registers and Modules
    2. 10.2 Typical Applications
      1. 10.2.1 2.0 (Stereo BTL) System
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Step One: Hardware Integration
          2. 10.2.1.2.2 Step Two: System Level Tuning
          3. 10.2.1.2.3 Step Three: Software Integration
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Mono (PBTL) Systems
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Step One: Hardware Integration
          2. 10.2.2.2.2 Step Two: System Level Tuning
          3. 10.2.2.2.3 Step Three: Software Integration
        3. 10.2.2.3 Application Specific Performance Plots for Mono (PBTL) Systems
      3. 10.2.3 2.1 (Stereo BTL + External Mono Amplifier) Systems
        1. 10.2.3.1 Advanced 2.1 System (Two TAS5780M devices)
        2. 10.2.3.2 Design Requirements
        3. 10.2.3.3 Application Specific Performance Plots for 2.1 (Stereo BTL + External Mono Amplifier) Systems
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
      1. 11.1.1 DVDD Supply
      2. 11.1.2 PVDD Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 General Guidelines for Audio Amplifiers
      2. 12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 12.1.3 Optimizing Thermal Performance
        1. 12.1.3.1 Device, Copper, and Component Layout
        2. 12.1.3.2 Stencil Pattern
          1. 12.1.3.2.1 PCB footprint and Via Arrangement
            1. 12.1.3.2.1.1 Solder Stencil
    2. 12.2 Layout Example
      1. 12.2.1 2.0 (Stereo BTL) System
      2. 12.2.2 Mono (PBTL) System
      3. 12.2.3 2.1 (Stereo BTL + Mono PBTL) Systems
  13. 13Register Maps
    1. 13.1 Registers - Page 0
      1. 13.1.1   Register 1 (0x01)
      2. 13.1.2   Register 2 (0x02)
      3. 13.1.3   Register 3 (0x03)
      4. 13.1.4   Register 4 (0x04)
      5. 13.1.5   Register 5 (0x05)
      6. 13.1.6   Register 6 (0x06)
      7. 13.1.7   Register 7 (0x07)
      8. 13.1.8   Register 8 (0x08)
      9. 13.1.9   Register 9 (0x09)
      10. 13.1.10  Register 10 (0x0A)
      11. 13.1.11  Register 12 (0x0C)
      12. 13.1.12  Register 13 (0x0D)
      13. 13.1.13  Register 14 (0x0E)
      14. 13.1.14  Register 15 (0x0F)
      15. 13.1.15  Register 16 (0x10)
      16. 13.1.16  Register 17 (0x11)
      17. 13.1.17  Register 18 (0x12)
      18. 13.1.18  Register 19 (0x13)
      19. 13.1.19  Register 20 (0x14)
      20. 13.1.20  Register 21 (0x15)
      21. 13.1.21  Register 22 (0x16)
      22. 13.1.22  Register 23 (0x17)
      23. 13.1.23  Register 24 (0x18)
      24. 13.1.24  Register 25 (0x19)
      25. 13.1.25  Register 26 (0x1A)
      26. 13.1.26  Register 27 (0x1B)
      27. 13.1.27  Register 28 (0x1C)
      28. 13.1.28  Register 29 (0x1D)
      29. 13.1.29  Register 30 (0x1E)
      30. 13.1.30  Register 31 (0x1F)
      31. 13.1.31  Register 32 (0x20)
      32. 13.1.32  Register 33 (0x21)
      33. 13.1.33  Register 34 (0x22)
      34. 13.1.34  Register 35 (0x23)
      35. 13.1.35  Register 37 (0x25)
      36. 13.1.36  Register 38 (0x26)
      37. 13.1.37  Register 39 (0x27)
      38. 13.1.38  Register 40 (0x28)
      39. 13.1.39  Register 41 (0x29)
      40. 13.1.40  Register 42 (0x2A)
      41. 13.1.41  Register 43 (0x2B)
      42. 13.1.42  Register 44 (0x2C)
      43. 13.1.43  Register 45 (0x2D)
      44. 13.1.44  Register 46 (0x2E)
      45. 13.1.45  Register 47 (0x2F)
      46. 13.1.46  Register 48 (0x30)
      47. 13.1.47  Register 49 (0x31)
      48. 13.1.48  Register 50 (0x32)
      49. 13.1.49  Register 51 (0x33)
      50. 13.1.50  Register 52 (0x34)
      51. 13.1.51  Register 53 (0x35)
      52. 13.1.52  Register 59 (0x3B)
      53. 13.1.53  Register 60 (0x3C)
      54. 13.1.54  Register 61 (0x3D)
      55. 13.1.55  Register 62 (0x3E)
      56. 13.1.56  Register 63 (0x3F)
      57. 13.1.57  Register 64 (0x40)
      58. 13.1.58  Register 65 (0x41)
      59. 13.1.59  Register 66 (0x42)
      60. 13.1.60  Register 67 (0x43)
      61. 13.1.61  Register 68 (0x44)
      62. 13.1.62  Register 69 (0x45)
      63. 13.1.63  Register 70 (0x46)
      64. 13.1.64  Register 71 (0x47)
      65. 13.1.65  Register 72 (0x48)
      66. 13.1.66  Register 73 (0x49)
      67. 13.1.67  Register 74 (0x4A)
      68. 13.1.68  Register 75 (0x4B)
      69. 13.1.69  Register 76 (0x4C)
      70. 13.1.70  Register 78 (0x4E)
      71. 13.1.71  Register 79 (0x4F)
      72. 13.1.72  Register 80 (0x50)
      73. 13.1.73  Register 81 (0x51)
      74. 13.1.74  Register 82 (0x52)
      75. 13.1.75  Register 83 (0x53)
      76. 13.1.76  Register 84 (0x54)
      77. 13.1.77  Register 85 (0x55)
      78. 13.1.78  Register 86 (0x56)
      79. 13.1.79  Register 87 (0x57)
      80. 13.1.80  Register 88 (0x58)
      81. 13.1.81  Register 89 (0x59)
      82. 13.1.82  Register 91 (0x5B)
      83. 13.1.83  Register 92 (0x5C)
      84. 13.1.84  Register 93 (0x5D)
      85. 13.1.85  Register 94 (0x5E)
      86. 13.1.86  Register 95 (0x5F)
      87. 13.1.87  Register 96 (0x60)
      88. 13.1.88  Register 97 (0x61)
      89. 13.1.89  Register 98 (0x62)
      90. 13.1.90  Register 99 (0x63)
      91. 13.1.91  Register 100 (0x64)
      92. 13.1.92  Register 101 (0x65)
      93. 13.1.93  Register 102 (0x66)
      94. 13.1.94  Register 103 (0x67)
      95. 13.1.95  Register 104 (0x68)
      96. 13.1.96  Register 105 (0x69)
      97. 13.1.97  Register 106 (0x6A)
      98. 13.1.98  Register 107 (0x6B)
      99. 13.1.99  Register 108 (0x6C)
      100. 13.1.100 Register 109 (0x6D)
      101. 13.1.101 Register 110 (0x6E)
      102. 13.1.102 Register 111 (0x6F)
      103. 13.1.103 Register 112 (0x70)
      104. 13.1.104 Register 113 (0x71)
      105. 13.1.105 Register 114 (0x72)
      106. 13.1.106 Register 115 (0x73)
      107. 13.1.107 Register 118 (0x76)
      108. 13.1.108 Register 119 (0x77)
      109. 13.1.109 Register 120 (0x78)
      110. 13.1.110 Register 121 (0x79)
    2. 13.2 Registers - Page 1
      1. 13.2.1  Register 1 (0x01)
      2. 13.2.2  Register 2 (0x02)
      3. 13.2.3  Register 3 (0x03)
      4. 13.2.4  Register 4 (0x04)
      5. 13.2.5  Register 5 (0x05)
      6. 13.2.6  Register 6 (0x06)
      7. 13.2.7  Register 7 (0x07)
      8. 13.2.8  Register 8 (0x08)
      9. 13.2.9  Register 9 (0x09)
      10. 13.2.10 Register 10 (0x0A)
      11. 13.2.11 Register 11 (0x0B)
      12. 13.2.12 Register 12 (0x0C)
      13. 13.2.13 Register 13 (0x0D)
      14. 13.2.14 Register 14 (0x0E)
      15. 13.2.15 Register 15 (0x0F)
    3. 13.3 Registers - Page 253
      1. 13.3.1  Register 1 (0x01)
      2. 13.3.2  Register 2 (0x02)
      3. 13.3.3  Register 3 (0x03)
      4. 13.3.4  Register 4 (0x04)
      5. 13.3.5  Register 5 (0x05)
      6. 13.3.6  Register 6 (0x06)
      7. 13.3.7  Register 7 (0x07)
      8. 13.3.8  Register 8 (0x08)
      9. 13.3.9  Register 9 (0x09)
      10. 13.3.10 Register 10 (0x0A)
      11. 13.3.11 Register 11 (0x0B)
      12. 13.3.12 Register 12 (0x0C)
      13. 13.3.13 Register 13 (0x0D)
      14. 13.3.14 Register 14 (0x0E)
      15. 13.3.15 Register 15 (0x0F)
      16. 13.3.16 Register 16 (0x10)
      17. 13.3.17 Register 17 (0x11)
      18. 13.3.18 Register 18 (0x12)
      19. 13.3.19 Register 19 (0x13)
      20. 13.3.20 Register 20 (0x14)
      21. 13.3.21 Register 21 (0x15)
      22. 13.3.22 Register 2 (0x16)
      23. 13.3.23 Register 23 (0x17)
      24. 13.3.24 Register 24 (0x18)
      25. 13.3.25 Register 25 (0x19)
      26. 13.3.26 Register 26 (0x1A)
      27. 13.3.27 Register 27 (0x1B)
      28. 13.3.28 Register 28 (0x1C)
      29. 13.3.29 Register 29 (0x1D)
      30. 13.3.30 Register 30 (0x1E)
      31. 13.3.31 Register 31 (0x1F)
      32. 13.3.32 Register 32 (0x20)
      33. 13.3.33 Register 33 (0x21)
      34. 13.3.34 Register 34 (0x22)
      35. 13.3.35 Register 35 (0x23)
      36. 13.3.36 Register 36 (0x24)
      37. 13.3.37 Register 37 (0x25)
      38. 13.3.38 Register 38 (0x26)
      39. 13.3.39 Register 39 (0x27)
      40. 13.3.40 Register 40 (0x28)
      41. 13.3.41 Register 41 (0x29)
      42. 13.3.42 Register 42 (0x2A)
      43. 13.3.43 Register 43 (0x2B)
      44. 13.3.44 Register 44 (0x2C)
      45. 13.3.45 Register 63 (0x3F)
      46. 13.3.46 Register 64 (0x40)
      47. 13.3.47 Register 65 (0x41)
      48. 13.3.48 Register 70 (0x46)
      49. 13.3.49 Register 71 (0x47)
      50. 13.3.50 Register 72 (0x48)
      51. 13.3.51 Register 73 (0x49)
      52. 13.3.52 Register 74 (0x4A)
      53. 13.3.53 Register 75 (0x4B)
      54. 13.3.54 Register 76 (0x4C)
      55. 13.3.55 Register 77 (0x4D)
      56. 13.3.56 Register 78 (0x4E)
      57. 13.3.57 Register 79 (0x4F)
      58. 13.3.58 Register 80 (0x50)
      59. 13.3.59 Register 81 (0x51)
      60. 13.3.60 Register 82 (0x52)
      61. 13.3.61 Register 83 (0x53)
      62. 13.3.62 Register 84 (0x54)
      63. 13.3.63 Register 85 (0x55)
      64. 13.3.64 Register 86 (0x56)
      65. 13.3.65 Register 87 (0x57)
      66. 13.3.66 Register 88 (0x58)
      67. 13.3.67 Register 89 (0x59)
      68. 13.3.68 Register 90 (0x5A)
      69. 13.3.69 Register 91 (0x5B)
      70. 13.3.70 Register 92 (0x5C)
      71. 13.3.71 Register 93 (0x5D)
    4. 13.4 DSP Memory Map
  14. 14器件和文档支持
    1. 14.1 器件支持
      1. 14.1.1 器件命名规则
      2. 14.1.2 开发支持
    2. 14.2 接收文档更新通知
    3. 14.3 社区资源
    4. 14.4 商标
    5. 14.5 静电放电警告
    6. 14.6 Glossary
  15. 15机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

DCA Package
48-Pin TSSOP with PowerPAD™
Top View
TAS5780M pin_diag_ppad_slased7.gif

Pin Functions

PIN TYPE(1) INTERNAL TERMINATION DESCRIPTION
NAME NO.
ADR0 26 DI Sets the LSB of the I2C address to 0 if pulled to GND, to 1 if pulled to DVDD
ADR1 20 DI Sets the second LSB of the I2C address to 0 if pulled to GND, to 1 if pulled to DVDD
AGND 10 G — Ground reference for analog circuitry(2)
15
AVDD 14 P Figure 2 Power supply for internal analog circuitry
BSTRPA– 1 P Figure 3 Connection point for the SPK_OUTA– bootstrap capacitor which is used to create a power supply for the high-side gate drive for SPK_OUTA–
BSTRPA+ 5 P Connection point for the SPK_OUTA+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for SPK_OUTA+
BSTRPB– 48 P Connection point for the SPK_OUTB– bootstrap capacitor which is used to create a power supply for the high-side gate drive for SPK_OUTB–
BSTRPB+ 44 P Connection point for the SPK_OUTB+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for SPK_OUTB+
CN 34 P Figure 14 Negative pin for capacitor connection used in the line-driver charge pump
CP 32 P Figure 13 Positive pin for capacitor connection used in the line-driver charge pump
CPVDD 31 P Figure 2 Power supply for charge pump circuitry
CPVSS 35 P Figure 14 –3.3-V supply generated by charge pump for the DAC
DAC_OUTA 13 AO Figure 8 Single-ended output for Channel A of the DAC
DAC_OUTB 36 AO Single-ended output for Channel B of the DAC
DGND 29 G — Ground reference for digital circuitry. Connect this pin to the system ground.
DVDD 30 P Figure 2 Power supply for the internal digital circuitry
DVDD_REG 28 P Figure 15 Voltage regulator derived from DVDD supply for use for internal digital circuitry. This pin is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry.
GND 33 G — Ground pin for device. This pin should be connected to the system ground.
GPIO0 18 DI/O General purpose input/output pins (GPIOx). Refer to GPIO registers for configuration.
GPIO2 21
GVDD_REG 8 P Figure 5 Voltage regulator derived from PVDD supply to generate the voltage required for the gate drive of output MOSFETs. This pin is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry.
LRCK/FS 25 DI/O Figure 11 Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ, and RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync boundary.
MCLK 22 DI Master clock used for internal clock tree and sub-circuit and state machine clocking
PGND 3 G — Ground reference for power device circuitry. Connect this pin to the system ground.
39
46
PVDD 6 P Figure 1 Power supply for internal power circuitry
7
41
42
43
RESET 19 DI Figure 17 Device reset input. Pull down to reset, pull up to activate device.
SCL 17 DI Figure 10 I2C serial control port clock
SCLK 23 DI/O Figure 11 Bit clock for the digital signal that is active on the input data line of the serial data port
SDA 16 DI/O Figure 9 I2C serial control port data
SDIN 24 D1 Figure 11 Data line to the serial data port
SPK_INA– 11 AI Figure 7 Negative pin for differential speaker amplifier input A
SPK_INA+ 12 AI Positive pin for differential speaker amplifier input A
SPK_INB– 38 AI Negative pin for differential speaker amplifier input B
SPK_INB+ 37 AI Positive pin for differential speaker amplifier input B
SPK_FAULT 40 DO Figure 16 Fault pin which is pulled low when an overcurrent or overtemperature fault occurs
SPK_GAIN/FREQ 9 AI Figure 6 Sets the gain and switching frequency of the speaker amplifier, latched in upon start-up of the device.
SPK_OUTA– 2 AO Figure 4 Negative pin for differential speaker amplifier output A
SPK_OUTA+ 4 AO Positive pin for differential speaker amplifier output A
SPK_OUTB– 47 AO Negative pin for differential speaker amplifier output B
SPK_OUTB+ 45 AO Positive pin for differential speaker amplifier output B
SPK_MUTE 27 I Figure 12 Speaker amplifier mute which must be pulled low (connected to DGND) to mute the device and pulled high (connected to DVDD) to unmute the device.
PowerPAD — G — Provides both electrical and thermal connection from the device to the board. A matching ground pad must be provided on the PCB and the device connected to it through solder. For proper electrical operation, this ground pad must be connected to the system ground.
(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P = Power, G = Ground (0 V)
(2) This pin should be connected to the system ground.

6.1 Internal Pin Configurations

TAS5780M io_equivalents_pin06.gif Figure 1. PVDD Pins
TAS5780M io_equivalents_pin01.gif Figure 3. BSTRPxx Pins
TAS5780M io_equivalents_pin08.gif Figure 5. GVDD_REG Pin
TAS5780M io_equivalents_pin11.gif Figure 7. SPK_INxx Pins
TAS5780M io_equivalents_pin16.gif Figure 9. SDA Pin
TAS5780M io_equivalents_pin22.gif Figure 11. SCLK, BCLK, SDIN, and LRCK/FS Pins
TAS5780M io_equivalents_pin32.gif Figure 13. CP Pin
TAS5780M io_equivalents_pin28.gif Figure 15. DVDD_REG Pin
TAS5780M io_equivalents_pin19.gif Figure 17. RESET Pin
TAS5780M io_equivalents_pin14.gif Figure 2. AVDD, DVDD and CPVDD Pins
TAS5780M io_equivalents_pin02.gif Figure 4. SPK_OUTxx Pins
TAS5780M io_equivalents_pin09.gif Figure 6. SPK_GAIN/FREQ Pin
TAS5780M io_equivalents_pin13.gif Figure 8. DAC_OUTx Pins
TAS5780M io_equivalents_pin17.gif Figure 10. SCL Pin
TAS5780M io_equivalents_pin27.gif Figure 12. SPK_MUTE Pin
TAS5780M io_equivalents_pin34.gif Figure 14. CN and CPVSS Pins
TAS5780M io_equivalents_pin40.gif Figure 16. SPK_FAULT Pin