ZHCSFY4 数据表 | 德州仪器 TI.com.cn

ZHCSFY4 December 2016 TAS5780M

PRODUCTION DATA.

封装选项

13 Register Maps

13.1 Registers - Page 0

13.1.1 Register 1 (0x01)

Figure 94. Register 1 (0x01)

7	6	5	4	3	2	1	0
Reserved			RSTM	Reserved			RSTR
R/W			R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 34. Register 1 (0x01) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved			Reserved
4	RSTM	R/W	0	Reset Modules – This bit resets the interpolation filter and the DAC modules. Since the DSP is also reset, the coeffient RAM content will also be cleared by the DSP. This bit is auto cleared and can be set only in standby mode. 0: Normal 1: Reset modules
3-1	Reserved			Reserved
0	RSTR	R/W	0	Reset Registers – This bit resets the mode registers back to their initial values. The RAM content is not cleared, but the execution source will be back to ROM. This bit is auto cleared and must be set only when the DAC is in standby mode (resetting registers when the DAC is running is prohibited and not supported). 0: Normal 1: Reset mode registers

13.1.2 Register 2 (0x02)

Figure 95. Register 2 (0x02)

7	6	5	4	3	2	1	0
DSPR	Reserved		RQST	Reserved			RQPD
R/W	R/W		R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 35. Register 2 (0x02) Field Descriptions

Bit	Field	Type	Reset	Description
7	DSPR	R/W	1	DSP reset – When the bit is made 0, DSP will start powering up and send out data. This needs to be made 0 only after all the input clocks are (ASI,MCLK,PLLCLK) are settled so that DMA channels do not go out of sync. 0: Normal operation 1: Reset the DSP
6-5	Reserved	R/W		Reserved
4	RQST	R/W	0	Standby Request – When this bit is set, the DAC will be forced into a system standby mode, which is also the mode the system enters in the case of clock errors. In this mode, most subsystems will be powered down but the charge pump and digital power supply. 0: Normal operation 1: Standby mode
3-1	Reserved	R/W		Reserved
0	RQPD	R/W	0	Powerdown Request – When this bit is set, the DAC will be forced into powerdown mode, in which the power consumption would be minimum as the charge pump is also powered down. However, it will take longer to restart from this mode. This mode has higher precedence than the standby mode, i.e. setting this bit along with bit 4 for standby mode will result in the DAC going into powerdown mode. 0: Normal operation 1: Powerdown mode

13.1.3 Register 3 (0x03)

Figure 96. Register 3 (0x03)

7	6	5	4	3	2	1	0
SYNC	SDZE	SDZS	RQML	Reserved			RQMR
RO	RO	RO	R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 36. Register 3 (0x03) Field Descriptions

Bit	Field	Type	Reset	Description
7	SYNC	RO		sync_sig_to_dig – This is the clock signal to BackEnd. The clock frequency when device is running is 98.304 Mhz/1024 = 96 ksps
6	SDZE	RO		sdz_oe_to_dig – Backend IO buffer tristate signal. Will be asserted when LDO input and LDO output PORs are both detected 0: SYNC and SDZ buffers are tristated 1: SYNC and SDZ buffers are enabled
5	SDZS	RO		sdz_sig_to_dig – Backend Power up signal. Will be asserted when AVDD & CPVDD PORs are detected and Line amplifiers are unmuted 0: BackEnd is shutdown 1: BackEnd is powered up
4	RQML	R/W	0	Mute Left Channel – This bit issues soft mute request for the left channel. The volume will be smoothly ramped down/up to avoid pop/click noise. 0: Normal volume 1: Mute
3-1	Reserved	R/W		Reserved
0	RQMR	R/W	0	Mute Right Channel – This bit issues soft mute request for the right channel. The volume will be smoothly ramped down/up to avoid pop/click noise. 0: Normal volume 1: Mute

13.1.4 Register 4 (0x04)

Figure 97. Register 4 (0x04)

7	6	5	4	3	2	1	0
Reserved			PLCK	Reserved			PLLE
R/W			R	R/W			R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 37. Register 4 (0x04) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W		Reserved
4	PLCK	R	0	PLL Lock Flag – This bit indicates whether the PLL is locked or not. When the PLL is disabled this bit always shows that the PLL is not locked. 0: The PLL is locked 1: The PLL is not locked
3-1	Reserved	R/W		Reserved
0	PLLE	R	1	PLL Enable – This bit enables or disables the internal PLL. When PLL is disabled, the master clock will be switched to the MCLK. 0: Disable PLL 1: Enable PLL

13.1.5 Register 5 (0x05)

Figure 98. Register 5 (0x05)

7	6	5	4	3	2	1	0
Reserved		OSSL	OSPD	Reserved			OSAD
R/W		RO	RO	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 38. Register 5 (0x05) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R/W		Reserved
5	OSSL	RO		Oscillator Clock Selected – This bit, when set, indicates that the internal oscillator is being selected as the master clock and that the system is in emergency state where the normal system clock is not available/reliable. 0: Oscillator clock is not selected 1: Oscillator clock is being selected
4	OSPD	RO		Oscillator Powerdown Status – This bit, when set, indicates that the oscillator is being powered down, as a result of setting the oscillator to auto disable mode and the oscillator clock is not needed/selected. 0: Oscillator is active 1: Oscillator is powered down
3-1	Reserved	R/W		Reserved
0	OSAD	R/W	1	Oscillator Auto Disable – This bit sets the oscillator to auto disable mode, in which the oscillator is powered down when it is not needed anymore. By disabling the oscillator, both power consumption and potential interference is reduced. 0: Oscillator is always active 1: Oscillator is auto disabled (Powered down when not in use)

13.1.6 Register 6 (0x06)

Figure 99. Register 6 (0x06)

7	6	5	4	3	2	1	0
Reserved			OI2C	DBPG	FRMD	FSMI	Reserved
R/W			R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 39. Register 6 (0x06) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved			Reserved
4	OI2C	R/W	0	old_i2c_mode_reg_r – In Hans, I2C is always in auto increment mode. In old device MSB during control word decides whether is auto-increment mode or not. Writing this bit as 1 enables the older mode. 0: Register Auto increment enabled by default 1: Register auto increment mode enabled based on the MSB value sent during address portion of I2C protocol
3	DBPG	R/W	0	Page auto increment disable – Disable page auto increment mode. for non -zero books. When end of page is reached it goes back to 8th address location of next page when this bit is 0. When this bit is 1 it goes to 0 th location of current page itself like in older part. 0: Enable Page auto increment 1: Disable Page auto increment
2	FRMD	R/W	0	SPI register read frame delay – When reading non-zero memory locations there is 1 frame delay between address and actual data. Which is read. By making this bit even for book0 register read there will be 1 frame delay to make it consistent across all books 0: No frame delay for SPI read for Book0 registers. 1: 1 frame delay for SPI read for Book0 registers.
1	FSMI	R/W	0	SPI MISO function sel: 00: SPI_MISO 01: GPIO3 Others: Reserved (Do not set)
0	Reserved	R/W	0	These bits select the function of the SPI_MISO pin when in SPI mode. If the pin is set as GPIO, register readout via SPI is not possible.

13.1.7 Register 7 (0x07)

Figure 100. Register 7 (0x07)

7	6	5	4	3	2	1	0
Reserved			DEMP	Reserved			SDSL
R/W			R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 40. Register 7 (0x07) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W		Reserved
4	DEMP	R/W	0	De-Emphasis Enable – This bit enables or disables the de-emphasis filter. The default coefficients are for 44.1 kHz sampling rate, but can be changed by reprogramming the appropriate coeffients in RAM. 0: De-emphasis filter is disabled 1: De-emphasis filter is enabled
3-1	Reserved	R/W		Reserved
0	SDSL	R/W	0	SDOUT Select – This bit selects what is being output as SDOUT via GPIO pins. 0: SDOUT is the DSP output (post-processing) 1: SDOUT is the DSP input (pre-processing)

13.1.8 Register 8 (0x08)

Figure 101. Register 8 (0x08)

7	6	5	4	3	2	1	0
Reserved		G2OE	MUTEOE	G0OE	Reserved
R/W		R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 41. Register 8 (0x08) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R/W		Reserved
5	G2OE	R/W	0	GPIO2 Output Enable – This bit sets the direction of the GPIO2 pin 0: GPIO2 is input 1: GPIO2 is output
4	MUTEOE	R/W	0	MUTE Control Enable – This bit sets an enable of MUTE control from PCM to TPA 0: MUTE control disable 1: MUTE control enable
3	G0OE	R/W	0	GPIO0 Output Enable – This bit sets the direction of the GPIO0 pin 0: GPIO0 is input 1: GPIO0 is output
2	Reserved	R/W	0	Reserved
1-0	Reserved	R/W	0	Reserved

13.1.9 Register 9 (0x09)

Figure 102. Register 9 (0x09)

7	6	5	4	3	2	1	0
Reserved		SCLKP	SCLKO	Reserved			LRCLKFSO
R/W		R/W	R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 42. Register 9 (0x09) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved			Reserved
5	SCLKP	R/W	0	SCLK Polarity – This bit sets the inverted SCLK mode. In inverted SCLK mode, the DAC assumes that the LRCLK and DIN edges are aligned to the rising edge of the SCLK. Normally they are assumed to be aligned to the falling edge of the SCLK. 0: Normal SCLK mode 1: Inverted SCLK mode
4	SCLKO	R/W	0	SCLK Output Enable – This bit sets the SCLK pin direction to output for I2S master mode operation. In I2S master mode the PCM51xx outputs the reference SCLK and LRCLK, and the external source device provides the DIN according to these clocks. Use P0-R32 to program the division factor of the MCLK to yield the desired SCLK rate (normally 64 FS) 0: SCLK is input (I2S slave mode) 1: SCLK is output (I2S master mode)
3-1	Reserved			Reserved
0	LRKO	R/W	0	LRCLK Output Enable – This bit sets the LRCLK pin direction to output for I2S master mode operation. In I2S master mode the PCM51xx outputs the reference SCLK and LRCLK, and the external source device provides the DIN according to these clocks. Use P0-R33 to program the division factor of the SCLK to yield 1 FS for LRCLK. 0: LRCLK is input (I2S slave mode) 1: LRCLK is output (I2S master mode)

13.1.10 Register 10 (0x0A)

Figure 103. Register 10 (0x0A)

7	6	5	4	3	2	1	0
DSPG	Reserved
R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 43. Register 10 (0x0A) Field Descriptions

Bit	Field	Type	Reset	Description
7	DSPG	R/W	0	DSP GPIO Input – this 8 bit bus reaches the DSP input port. DSP s/w can access these bits for getting any direct control/input from host ny means of this register write
6-0	Reserved	R/W	0	Reserved

13.1.11 Register 12 (0x0C)

Figure 104. Register 12 (0x0C)

7	6	5	4	3	2	1	0
Reserved	RDSP	RDAC	RNCP	ROSR	RSYN	RSCLK	RLRK
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 44. Register 12 (0x0C) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W		Reserved
6	RDSP	R/W	1	RST uCDSP clock – This bit, when set to 0 will reset the DSP clock divider and thus, halt the DSP clock. 0: DSP clock divider is reset 1: DSP clock divider is functional
5	RDAC	R/W	1	RST DAC clock – This bit, when set to 0 will reset the DAC clock divider and thus, halt the DAC clock and its derivatives. 0: DAC clock divider is reset 1: DAC clock divider is functional
4	RNCP	R/W	1	RST NCP clock – This bit, when set to 0 will reset the OSR clock divider and thus, halt the OSR clock. 0: OSR clock divider is reset 1: OSR clock divider is functional
3	ROSR	R/W	1	RSTOSR clock – This bit, when set to 0 will reset the clock synchronizer and thus, halt the DAC clock and its derivatives. When this bit is set to 1, the dividers un-reset will take place synchronized to the beginning of audio frame. 0: DAC clock and its derivatives are stopped asynchronously 1: DAC clock and its derivatives started synchronized to the beginning of audio frame
2	RSYN	R/W	1	RST clock sync – This bit, when set to 0 will reset the clock synchronizer and thus, halt the DAC clock and its derivatives. When this bit is set to 1, the dividers un-reset will take place synchronized to the beginning of audio frame. 0: DAC clock and its derivatives are stopped asynchronously 1: DAC clock and its derivatives started synchronized to the beginning of audio frame
1	RSCLK	R/W	0	Master Mode SCLK Divider Reset – This bit, when set to 0, will reset the MCLK divider to generate SCLK clock for I2S master mode. To use I2S master mode, the divider must be enabled and programmed properly. 0: Master mode SCLK clock divider is reset 1: Master mode SCLK clock divider is functional
0	RLRK	R/W	1	Master Mode LRCLK Divider Reset – This bit, when set to 0, will reset the SCLK divider to generate LRCLK clock for I2S master mode. To use I2S master mode, the divider must be enabled and programmed properly. 0: Master mode LRCLK clock divider is reset 1: Master mode LRCLK clock divider is functional

13.1.12 Register 13 (0x0D)

Figure 105. Register 13 (0x0D)

7	6	5	4	3	2	1	0
Reserved	SREF		SREF	Reserved	SDSP
R/W	R/W		R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 45. Register 13 (0x0D) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W		Reserved
6-5	SREF	R/W	0	PLL Reference:
4	SREF	R/W	0	DSP clock source – This bit select the source clock for internal PLL. This bit is ignored and overriden in clock auto set mode. 0: The PLL reference clock is MCLK 1: The PLL reference clock is SCLK 010: The PLL reference clock is oscillator clock 011: The PLL reference clock is GPIO (selected using P0-R18) Others: Reserved (PLL reference is muted)
3	Reserved	R/W		Reserved
2-0	SDSP	R/W	0	DAC clock source – These bits select the source clock for DSP clock divider. 000: Master clock (PLL/MCLK and OSC auto-select) 001: PLL clock 010: OSC clock 011: MCLK clock 100: SCLK clock 101: GPIO (selected using P0-R16) Others: Reserved (muted)

13.1.13 Register 14 (0x0E)

Figure 106. Register 14 (0x0E)

7	6	5	4	3	2	1	0
Reserved	SDAC			Reserved	SOSR
R/W	R/W			R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 46. Register 14 (0x0E) Field Descriptions

Bit	Field	Type	Description
7	Reserved	R/W	Reserved
6-4	SDAC	R/W	DAC clock source – These bits select the source clock for DAC clock divider. 000: Master clock (PLL/MCLK and OSC auto-select) 001: PLL clock 010: OSC clock 011: MCLK clock 100: SCLK clock 101: GPIO (selected using P0-R16) Others: Reserved (muted)
3	Reserved	R/W	Reserved
2-0	SOSR	R/W	OSR clock source – These bits select the source clock for OSR clock divider. 000: DAC clock 001: Master clock (PLL/MCLK and OSC auto-select) 010: PLL clock 011: OSC clock 100: MCLK clock 101: SCLK clock 110: GPIO (selected using P0-R17) Others: Reserved (muted)

13.1.14 Register 15 (0x0F)

Figure 107. Register 15 (0x0F)

7	6	5	4	3	2	1	0
Reserved					SNCP
R/W					R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 47. Register 15 (0x0F) Field Descriptions

Bit	Field	Type	Reset	Description
7-3	Reserved	R/W		Reserved
2-0	SNCP	R/W	0	NCP clock source – These bits select the source clock for CP clock divider. 000: DAC clock 001: Master clock (PLL/MCLK and OSC auto-select) 010: PLL clock 011: OSC clock 100: MCLK clock 101: SCLK clock 110: GPIO (selected using P0-R17) Others: Reserved (muted)

13.1.15 Register 16 (0x10)

Figure 108. Register 16 (0x10)

7	6	5	4	3	2	1	0
Reserved	GDSP			Reserved	GDAC
R/W	R/W			R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 48. Register 16 (0x10) Field Descriptions

Bit	Field	Type	Description
7	Reserved	R/W	Reserved
6-4	GDSP	R/W	GPIO Source for uCDSP clk – These bits select the GPIO pins as clock input source when GPIO is selected as DSP clock divider source. 000: N/A 001: N/A 010: N/A 011: GPIO0 100: N/A 101: GPIO2 Others: Reserved (muted)
3	Reserved	R/W	Reserved
2-0	GDAC	R/W	GPIO Source for DAC clk – These bits select the GPIO pins as clock input source when GPIO is selected as DAC clock divider source. 000: N/A 001: N/A 010: N/A 011: GPIO0 100: N/A 101: GPIO2 Others: Reserved (muted)

13.1.16 Register 17 (0x11)

Figure 109. Register 17 (0x11)

7	6	5	4	3	2	1	0
Reserved	GNCP			Reserved	GOSR
R/W	R/W			R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 49. Register 17 (0x11) Field Descriptions

Bit	Field	Type	Description
7	Reserved	R/W	Reserved
6-4	GNCP	R/W	GPIO Source for NCP clk – These bits select the GPIO pins as clock input source when GPIO is selected as CP clock divider source 000: N/A 001: N/A 010: Reserved 011: GPIO0 100: N/A 101: GPIO2 Others: Reserved (muted)
3	Reserved	R/W	Reserved
2-0	GOSR	R/W	GPIO Source for OSR clk – These bits select the GPIO pins as clock input source when GPIO is selected as OSR clock divider source. 000: N/A 001: N/A 010: Reserved 011: GPIO0 100: N/A 101: GPIO2 Others: Reserved (muted)

13.1.17 Register 18 (0x12)

Figure 110. Register 18 (0x12)

7	6	5	4	3	2	1	0
Reserved					GREF
R/W					R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 50. Register 18 (0x12) Field Descriptions

Bit	Field	Type	Reset	Description
7-3	Reserved	R/W	0	Reserved
2-0	GREF	R/W	0	GPIO Source for PLL reference clk – These bits select the GPIO pins as clock input source when GPIO is selected as the PLL reference clock source. 000: N/A 001: N/A 010: Reserved 011: GPIO0 100: N/A 101: GPIO2 Others: Reserved (muted)

13.1.18 Register 19 (0x13)

Figure 111. Register 19 (0x13)

7	6	5	4	3	2	1	0
Reserved			AREN	Reserved			RQSY
R/W			R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 51. Register 19 (0x13) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W		Reserved
4	AREN	R/W	1	Auto resync enable – This bits enables or disables the DAC/CP clock auto resynchronization with the beginning of audio frame. When enabled, the resynchronization is carried out just before the DAC transitions from standby mode to normal operation mode. 0: Auto resynchronization is disabled 1: Auto resynchronization is enabled
3-1	Reserved	R/W		Reserved
0	RQSY	R/W	0	This bit, when set to 1 will issue the clock resynchronization by synchronously resets the DAC, CP and OSR clocks. The actual clock resynchronization takes place when this bit is set back to 0, where the DAC, CP and OSR clocks are resumed at the beginning of the audio frame. 0: Resume DAC, CP and OSR clocks synchronized to the beginning of audio frame 1: Halt DAC, CP and OSR clocks as the beginning of resynchronization process

13.1.19 Register 20 (0x14)

Figure 112. Register 20 (0x14)

7	6	5	4	3	2	1	0
Reserved	PPDV				Reserved
R/W	R/W				R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 52. Register 20 (0x14) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W	0	Reserved
6-3	PPDV	R/W	0	PLL P – These bits set the PLL divider P factor. These bits are ignored in clock auto set mode. 0000: P=1 0001: P=2 ... 1110: P=15 1111: Prohibited (do not set this value)
2-1	Reserved	R/W	0	Reserved
0	Reserved	R/W	1	Reserved

13.1.20 Register 21 (0x15)

Figure 113. Register 21 (0x15)

7	6	5	4	3	2	1	0
Reserved		PJDV		Reserved			Reserved
R/W		R/W		R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 53. Register 21 (0x15) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved		0	Reserved
5-4	PJDV	P/W	0	PLL J – These bits set the J part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set mode. 000000: Prohibited (do not set this value) 000001: J=1 000010: J=2 ... 111111: J=63
3		P/W	1	Reserved
2-0		P/W	0	Reserved

13.1.21 Register 22 (0x16)

Figure 114. Register 22 (0x16)

7	6	5	4	3	2	1	0
Reserved		PDDV
R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 54. Register 22 (0x16) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R/W		Reserved
5-0	PDDV	R/W	0	PLL D (MSB) – These bits set the D part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set mode. 0 (in decimal): D=0000 1 (in decimal): D=0001 ... 9999 (in decimal): D=9999 Others: Prohibited (do not set)

13.1.22 Register 23 (0x17)

Figure 115. Register 23 (0x17)

7	6	5	4	3	2	1	0
PDDV
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 55. Register 23 (0x17) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PDDV	R/W	0	PLL D (LSB) – These bits set the D part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set mode. 0 (in decimal): D=0000 1 (in decimal): D=0001 ... 9999 (in decimal): D=9999 Others: Prohibited (do not set)

13.1.23 Register 24 (0x18)

Figure 116. Register 24 (0x18)

7	6	5	4	3	2	1	0
Reserved				PRDV
R/W				R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 56. Register 24 (0x18) Field Descriptions

Bit	Field	Type	Reset	Description
7-4	Reserved	R/W		Reserved
3-0	PRDV	R/W	0	PLL R – These bits set the R part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set mode. 0000: R=1 0001: R=2 ... 1111: R=16

13.1.24 Register 25 (0x19)

Figure 117. Register 25 (0x19)

7	6	5	4	3	2	1	0
PLCT
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 57. Register 25 (0x19) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PLCT	R/W	0	PLL Lock Count – These bits set the number of consecutive PLL lock flags counted by the feedback clock before PLL is declared locked. The count value is updated when addr 26 is written, so it is recommended to update addr 25 first and then addr 26.

13.1.25 Register 26 (0x1A)

Figure 118. Register 26 (0x1A)

7	6	5	4	3	2	1	0
PLCT
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 58. Register 26 (0x1A) Field Descriptions

Bit	Field	Type	Reset	Description
7	PLCT	R/W	1	PLL Lock Count – These bits set the number of consecutive PLL lock flags counted by the feedback clock before PLL is declared locked. The count value is updated when addr 26 is written, so it is recommended to update addr 25 first and then addr 26.
6-0	PLCT	R/W	0

13.1.26 Register 27 (0x1B)

Figure 119. Register 27 (0x1B)

7	6	5	4	3	2	1	0
Reserved	DDSP
R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 59. Register 27 (0x1B) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W		Reserved
6-0	DDSP	R/W	0	DSP Clock Divider – These bits set the source clock divider value for the DSP clock. These bits are ignored in clock auto set mode. 0000000: Divide by 1 0000001: Divide by 2 ... 1111111: Divide by 128

13.1.27 Register 28 (0x1C)

Figure 120. Register 28 (0x1C)

7	6	5	4	3	2	1	0
Reserved	DDAC
R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 60. Register 28 (0x1C) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved			Reserved
6-4	DDAC	R/W	0	DAC Clock Divider – These bits set the source clock divider value for the DAC clock. These bits are ignored in clock auto set mode. 0000000: Divide by 1 0000001: Divide by 2 ... 1111111: Divide by 128
3-0	DDAC	R/W	1

13.1.28 Register 29 (0x1D)

Figure 121. Register 29 (0x1D)

7	6	5	4	3	2	1	0
Reserved	DNCP
R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 61. Register 29 (0x1D) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved			Reserved
6-2	DNCP	R/W	0	NCP Clock Divider – These bits set the source clock divider value for the CP clock. These bits are ignored in clock auto set mode. 0000000: Divide by 1 0000001: Divide by 2 ... 1111111: Divide by 128
1-0	DNCP	R/W	1

13.1.29 Register 30 (0x1E)

Figure 122. Register 30 (0x1E)

7	6	5	4	3	2	1	0
Reserved	DOSR
R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 62. Register 30 (0x1E) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved			Reserved
6-4	DOSR	R/W	0	OSR Clock Divider – These bits set the source clock divider value for the OSR clock. These bits are ignored in clock auto set mode. 0000000: Divide by 1 0000001: Divide by 2 ... 1111111: Divide by 128
5-0	DOSR	R/W	1

13.1.30 Register 31 (0x1F)

Figure 123. Register 31 (0x1F)

7	6	5	4	3	2	1	0
Reserved	DOFS
R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 63. Register 31 (0x1F) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved			Reserved
6-3	DOFS	R/W	0	Offset calibrator clock div – These bits set the source clock divider value for the offset calibrator 0000000: Divide by 1 0000001: Divide by 2 ... 1111111: Divide by 128
2		R/W	1
1-0		R/W	0

13.1.31 Register 32 (0x20)

Figure 124. Register 32 (0x20)

7	6	5	4	3	2	1	0
Reserved	DSCLK
R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 64. Register 32 (0x20) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W		Reserved
6-0	DSCLK	R/W	0	Master Mode SCLK Divider – These bits set the MCLK divider value to generate I2S master SCLK clock. 0000000: Divide by 1 0000001: Divide by 2 ... 1111111: Divide by 128

13.1.32 Register 33 (0x21)

Figure 125. Register 33 (0x21)

7	6	5	4	3	2	1	0
DLRK
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 65. Register 33 (0x21) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DLRK	R/W	0	Master Mode LRCLK Divider – These bits set the I2S master SCLK clock divider value to generate I2S master LRCLK clock 00000000: Divide by 1 00000001: Divide by 2 ... 11111111: Divide by 256

13.1.33 Register 34 (0x22)

Figure 126. Register 34 (0x22)

7	6	5	4	3	2	1	0
Reserved			I16E	Reserved	FSSP	FSSP
R/W			R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 66. Register 34 (0x22) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W		Reserved
4	I16E	R/W	0	16x Interpolation – This bit enables or disables the 16x interpolation mode 0: 8x interpolation 1: 16x interpolation
3	Reserved	R/W		Reserved
2	FSSP	R/W	1	FS Speed Mode – These bits select the FS operation mode, which must be set according to the current audio sampling rate. These bits are ignored in clock auto set mode. 000: Reserved 001: Reserved 010: Reserved 011: 48 kHz 100: 88.2-96 kHz 101: Reserved 110: Reserved 111: 32kHz
1-0	FSSP	R/W	0

13.1.34 Register 35 (0x23)

Figure 127. Register 35 (0x23)

7	6	5	4	3	2	1	0
Reserved							INTFLAG
R/W							R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 67. Register 35 (0x23) Field Descriptions

Bit	Field	Type	Reset	Description
7-1	Reserved	R/W	0	Reserved
0		R	0	Pin interrupt sticky flag – Sticky flag that reflects the pin interrupt value. Once read pin interrupt and this register will automatically reset to 0. To mask which all faults/errors can generate this interrupt use B0_P0_R45. 0: interrupt de-asserted 1: interrupt asserted

13.1.35 Register 37 (0x25)

Figure 128. Register 37 (0x25)

7	6	5	4	3	2	1	0
Reserved	IDFS	IDBK	IDSK	IDCH	IDCM	DCAS	IPLK
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 68. Register 37 (0x25) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W		Reserved
6	IDFS	R/W	0	Ignore FS Detection – This bit controls whether to ignore the FS detection. When ignored, FS error will not cause a clock error. 0: Regard FS detection 1: Ignore FS detection
5	IDBK	R/W	0	Ignore SCLK Detection – This bit controls whether to ignore the SCLK detection against LRCLK. The SCLK must be stable between 32 FS and 256 FS inclusive or an error will be reported. When ignored, a SCLK error will not cause a clock error. 0: Regard SCLK detection 1: Ignore SCLK detection
4	IDSK	R/W	0	Ignore MCLK Detection – This bit controls whether to ignore the MCLK detection against LRCLK. Only some certain MCLK ratios within some error margin are allowed. When ignored, an MCLK error will not cause a clock error. 0: Regard MCLK detection 1: Ignore MCLK detection
3	IDCH	R/W	0	Ignore Clock Halt Detection – This bit controls whether to ignore the MCLK halt (static or frequency is lower than acceptable) detection. When ignored an MCLK halt will not cause a clock error. 0: Regard MCLK halt detection 1: Ignore MCLK halt detection
2	IDCM	R/W	0	Ignore LRCLK/SCLK Missing Detection – This bit controls whether to ignore the LRCLK/SCLK missing detection. The LRCLK/SCLK need to be in low state (not only static) to be deemed missing. When ignored an LRCLK/SCLK missing will not cause the DAC go into powerdown mode. 0: Regard LRCLK/SCLK missing detection 1: Ignore LRCLK/SCLK missing detection
1	DCAS	R/W	0	Disable Clock Divider Autoset – This bit enables or disables the clock auto set mode. When dealing with uncommon audio clock configuration, the auto set mode must be disabled and all clock dividers must be set manually. Addtionally, some clock detectors might also need to be disabled. The clock autoset feature will not work with PLL enabled in VCOM mode. In this case this feature has to be disabled and the clock dividers must be set manually. 0: Enable clock auto set 1: Disable clock auto set
0	IPLK	R/W	0	Ignore PLL Lock Detection – This bit controls whether to ignore the PLL lock detection. When ignored, PLL unlocks will not cause a clock error. The PLL lock flag at P0-R4, bit 4 is always correct regardless of this bit. 0: PLL unlocks raise clock error 1: PLL unlocks are ignored

13.1.36 Register 38 (0x26)

Figure 129. Register 38 (0x26)

7	6	5	4	3	2	1	0
BKCG				BKCB
R/W				R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 69. Register 38 (0x26) Field Descriptions

Bit	Field	Type	Reset	Description
7-4	BKCG	R/W	1	BCLK count to good – These bits specify the number of consecutive valid SCLK counts in LRCLK until the SCLK is deemed good. To be valid, the SCLK counts in LRCLK should be between 32 and 256 inclusive and match the count at previous audio frame. 0000: One consecutive LRCLK 0001: Two consecutive LRCLKs ... 1111: 16 consecutive LRCLKs
3-2	BKCB	R/W	0	BCLK count to bad – These bits specify the number of consecutive invalid SCLK counts in LRCLK until the SCLK is deemed bad. To be valid, the SCLK counts in LRCLK should be between 32 and 256 inclusive and match the count at previous audio frame. 0000: One consecutive LRCLK 0001: Two consecutive LRCLKs ... 1111: 16 consecutive LRCLKs
1-0	BKCB	R/W	1

13.1.37 Register 39 (0x27)

Figure 130. Register 39 (0x27)

7	6	5	4	3	2	1	0
Reserved			MCLKT
R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 70. Register 39 (0x27) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W		Reserved
4-3	MCLKT	R/W	0	MCLK tolerance – These bits specify the tolerance for MCLK counts in LRCLK. When the MCLK count in LRCLK matches any valid ratio within this tolerance, it will be deemed good 00000: tolerate ± 0 count 00001: tolerate ± 1 count … 11111: tolerate ± 31 counts
2		R/W	1
1-0		R/W	0

13.1.38 Register 40 (0x28)

Figure 131. Register 40 (0x28)

7	6	5	4	3	2	1	0
Reserved		AFMT		Reserved		ALEN
R/W		R/W		R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 71. Register 40 (0x28) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	–
5-4	AFMT	R/W	0	I2S Data Format – These bits control both input and output audio interface formats for DAC operation. 00: I2S 01: DSP 10: RTJ 11: LTJ
3-2	Reserved	R/W		Reserved
1	ALEN	R/W	1	I2S Word Length – These bits control both input and output audio interface sample word lengths for DAC operation. 00: 16 bits 01: 20 bits 10: 24 bits 11: 32 bits
0	ALEN	R/W	0

13.1.39 Register 41 (0x29)

Figure 132. Register 41 (0x29)

7	6	5	4	3	2	1	0
AOFS
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 72. Register 41 (0x29) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	AOFS	R/W	0	I2S Shift – These bits control the offset of audio data in the audio frame for both input and output. The offset is defined as the number of SCLK from the starting (MSB) of audio frame to the starting of the desired audio sample. 00000000: offset = 0 SCLK (no offset) 00000001: ofsset = 1 SCLK 00000010: offset = 2 SCLKs … 11111111: offset = 256 SCLKs

13.1.40 Register 42 (0x2A)

Figure 133. Register 42 (0x2A)

7	6	5	4	3	2	1	0
Reserved		AUPL		Reserved		AUPR
R/W		R/W		R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 73. Register 42 (0x2A) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R/W		Reserved
5	AUPL	R/W	0	Left DAC Data Path – These bits control the left channel audio data path connection. 00: Zero data (mute) 01: Left channel data 10: Right channel data 11: Reserved (do not set)
4		R/W	1
3-2	Reserved	R/W		Reserved
1	AUPR	R/W	0	Right DAC Data Path – These bits control the right channel audio data path connection. 00: Zero data (mute) 01: Right channel data 10: Left channel data 11: Reserved (do not set)
0		R/W	1

13.1.41 Register 43 (0x2B)

Figure 134. Register 43 (0x2B)

7	6	5	4	3	2	1	0
Reserved			PSEL
R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 74. Register 43 (0x2B) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W		Reserved
4-1	PSEL	R/W	0	DSP Program Selection – These bits select the DSP program to use for audio processing. 00000: Reserved 00001: Rom Mode 1 00010: Reserved 00011: Reserved
0		R/W	1

13.1.42 Register 44 (0x2C)

Figure 135. Register 44 (0x2C)

7	6	5	4	3	2	1	0
Reserved				CLKM	CMDP
R/W				R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 75. Register 44 (0x2C) Field Descriptions

Bit	Field	Type	Reset	Description
7-4	Reserved			Reserved
3	CLKM	R/W	1	clk_missing_mode_hans_reg_r – Fallback option to change clock missing detection to older PCM device. In Hans clock missing is detected whenever either BCLK or LRCLK go missing. In older PCM device clock missing is detected whenever LRCLK or BCLK are stuck to 1. 0 : Old mode of ASI clock missing detection 1: Hans mode of ASI clock missing detect
2-0	CMDP	R/W	0	Clock Missing Detection Period – These bits set how long both SCLK and LRCLK keep low before the audio clocks deemed missing and the DAC transitions to powerdown mode. 000: about 1 second 001: about 2 seconds 010: about 3 seconds ... 111: about 8 seconds

13.1.43 Register 45 (0x2D)

Figure 136. Register 45 (0x2D)

7	6	5	4	3	2	1	0
MSKP
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 76. Register 45 (0x2D) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

MSKP

R/W

Mask for Pin interrupt generated by device (?)

To mask and selectively use the required faults alone to generate the interrupt

0 : No interrupt generated
1 : Allow interrupt to be generated

1 : No interrupt generated
1 : Allow interrupt to be generated

2 : No interrupt generated
1 : Allow interrupt to be generated

3 : No interrupt generated
1 : Allow interrupt to be generated

4 : No interrupt generated
1 : Allow interrupt to be generated

5 : No interrupt generated
1 : Allow interrupt to be generated

Mask for Pin interrupt generated by device (short-flag)

6 : No interrupt generated
1 : Allow interrupt to be generated

Mask for Pin interrupt generated by device (dsp_interrupt)

7 : No interrupt generated
1 : Allow interrupt to be generated

13.1.44 Register 46 (0x2E)

Figure 137. Register 46 (0x2E)

7	6	5	4	3	2	1	0
Reserved							SDZF
R/W							R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 77. Register 46 (0x2E) Field Descriptions

Bit	Field	Type	Reset	Description
7-1	Reserved	R/W		Reserved
0	SDZF	R/W	1	Disable Force shutdown of Backend – This controls the Backed device shutdown signal. When it is programmed 0 backend devi ce will be shutdown. 0 : Force shutdown of Backend 1 : Disable force shutdown of Backend

13.1.45 Register 47 (0x2F)

Figure 138. Register 47 (0x2F)

7	6	5	4	3	2	1	0
Reserved		DLSH	Reserved
R/W		R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 78. Register 47 (0x2F) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R/W		Reserved
5	DLSH	R/W	0	Disable Last Sample Hold – This bit controls whether to hold the last sample at audio interface in the event of clock error. The last known good sample is held to prevent errorneous samples to flow through the DAC. 0: Enable last sample hold 1: Disable last sample hold
4-0	Reserved	R/W		Reserved

13.1.46 Register 48 (0x30)

Figure 139. Register 48 (0x30)

7	6	5	4	3	2	1	0
Reserved	EDINT	INTSTAT	INTGPIO			DBCLK
R/W	R/W	R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 79. Register 48 (0x30) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved			Reserved
6	EDINT	R/W	1	Edge detection of pin interrupt input – this bit controls whether to detect a positive edge and send interrupt to dsp or reflect the pin value at the dsp_interrupt port 0: disable positive edge detect 1: enable positive edge detect
5	INTSTAT	R/W	0	Enable active low for input pin interrupt – This controls whether input pin interrupt is active low or active high. 0 : input pin interrupt is active high 1 : input pin interrupt is active low
4-2	INTGPIO	R/W	0	GPIO for input pin interrupt – these bits control which GPIO to be used as the input pin interrupt 000: pin interrupt disabled 001: pin interrupt = Input from RESERVED 010: pin interrupt = Input from RESERVED 011: Reserved 100: pin interrupt = Input from GPIO0 101: pin interrupt = Input from RESERVED 110: pin interrupt = Input from GPIO2 111: reserved
1-0	DBCLK	R/W	0	Pin debounce clock select – selects the clk frequency to be used for deboucing glitches on pin before detecting a flip on the pin ( debouncing is done for 4 clock cycles of this selected clock) 00: approx 1 ms clk used for debouncing 01: approx 500 µs clk used for debouncing 10: approx 125 µs clk used for debouncing 11: oscillator clk used for debouncing

13.1.47 Register 49 (0x31)

Figure 140. Register 49 (0x31)

7	6	5	4	3	2	1	0
Reserved	GSPGPI2	Reserved	GSPGPI0	GSPGPI1	Reserved
R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 80. Register 49 (0x31) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W	0	Reserved
6	GSPGPI2	R/W	0	Enable GPIO2 value to propagate to DSP – Each bit when set high allows the corresponding GPIO pin value to propagate to DSP as an input port bus 0 : GPIO2 value will not propagate to DSP 1 : GPIO2 value is allowed to propagate to DSP
5	Reserved	R/W		Reserved
4	GSPGPI0	R/W	0	Enable GPIO0 value to propagate to DSP – Each bit when set high allows the corresponding GPIO pin value to propagate to DSP as an input port bus 0 : GPIO0 value will not propagate to DSP 1 : GPIO0 value is allowed to propagate to DSP
3-0	Reserved	R/W		Reserved

13.1.48 Register 50 (0x32)

Figure 141. Register 50 (0x32)

7	6	5	4	3	2	1	0
Reserved						DSPMEM	DSPCOEF
R/W						R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 81. Register 50 (0x32) Field Descriptions

Bit	Field	Type	Reset	Description
7-2	Reserved	R/W	0	Reserved
1	DSPMEM	R/W	0	DSP boots from IRAM – When set DSP will boot from IRAM instead of IROM 0: boot DSP from IROM 1: boot DSP from IRAM
0	DSPCOEF	R/W		Use default coefficients from ZROM – This bit controls whether to use default coefficients from ZROM or use the non-default coefficients downloaded to device by the Host 0 : don't use default coefficients from ZROM 1 : use default coefficents from ZROM

13.1.49 Register 51 (0x33)

Figure 142. Register 51 (0x33)

7	6	5	4	3	2	1	0
Reserved							DSPINT
R/W							R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 82. Register 51 (0x33) Field Descriptions

Bit	Field	Type	Reset	Description
7-1	Reserved	R/W		Reserved
0	DSPINT	R/W		Interrupt DSP – This bit can be set to generate an interrupt to DSP. Once the DSP acknowledges this interrupt this bit will be automatically cleared 0: normal 1 : generate interrupt to DSP

13.1.50 Register 52 (0x34)

Figure 143. Register 52 (0x34)

7	6	5	4	3	2	1	0
Reserved				DSPRMEM	MEMCRYP	MEMCRC
R/W				R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 83. (Register 52 (0x34) Field Descriptions

Bit	Field	Type	Description
7-4	Reserved	R/W	Reserved
3	DSPRMEM	R/W	Enable read from IRAM,IROM,ZROM – This bit controls whether to allow reads to IRAM, IROM and ZROM . When this bit is zero , read request to these memories will give out a 0 0 : dis-allow read from IRAM,IROM and ZROM 1 : all reads from IRAM, IROM and ZROM
2	MEMCRYP	R/W	Disable decryption – This bit controls whether to disable or enable decryption on the content that is downloaded by Host into IRAM 0 : enable decryption 1 : disable decryption
1-0	MEMCRC	R/W	CRC seed selection for Decryption – These bits control which seed to use for CRC based decryption logic. 00 : use A5 hex as seed 01 : use B6 hex as seed 10 : use 94 hex as seed 11 : use E2 hex as seed

13.1.51 Register 53 (0x35)

Figure 144. Register 53 (0x35)

7	6	5	4	3	2	1	0
Reserved							RSTD
R/W							R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 84. Register 53 (0x35) Field Descriptions

Bit	Field	Type	Reset	Description
7-1	Reserved	R/W		Reserved
0	RSTD	WO	0	Reset decryption block – Setting this bit to '1' resets the decryption block and reinitializes the CRC with the CRC seed. It is a self clearing bit. '1' -> reset the decryption block '0' -> decryption block is not reset

13.1.52 Register 59 (0x3B)

Figure 145. Register 59 (0x3B)

7	6	5	4	3	2	1	0
Reserved	AMTL			Reserved	AMTR
R/W	R/W			R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 85. Register 59 (0x3B) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W		Reserved
6-4	AMTL	R/W	0	Auto Mute Time for Left Channel – These bits specify the length of consecutive zero samples at left channel before the channel can be auto muted. The times shown are for 96 kHz sampling rate and will scale with other rates. 000: 11.5 ms 001: 53 ms 010: 106.5 ms 011: 266.5 ms 100: 0.535 sec 101: 1.065 sec 110: 2.665 sec 111: 5.33 sec
3	Reserved	R/W		Reserved
2-0	AMTR	R/W	0	Auto Mute Time for Right Channel – These bits specify the length of consecutive zero samples at right channel before the channel can be auto muted. The times shown are for 96 kHz sampling rate and will scale with other rates. 000: 11.5 ms 001: 53 ms 010: 106.5 ms 011: 266.5 ms 100: 0.535 sec 101: 1.065 sec 110: 2.665 sec 111: 5.33 sec

13.1.53 Register 60 (0x3C)

Figure 146. Register 60 (0x3C)

7	6	5	4	3	2	1	0
Reserved						PCTL
R/W						R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 86. Register 60 (0x3C) Field Descriptions

Bit	Field	Type	Reset	Description
7-2	Reserved	R/W	0	Reserved
1-0	PCTL	R/W	0	Digital Volume Control – These bits control the behavior of the digital volume. 00: The volume for Left and right channels are independent 01: Right channel volume follows left channel setting

13.1.54 Register 61 (0x3D)

Figure 147. Register 61 (0x3D)

7	6	5	4	3	2	1	0
VOLL
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 87. Register 61 (0x3D) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	VOLL	R/W	00010000	Left Digital Volume – These bits control the left channel digital volume. The digital volume is 24 dB to –103 dB in –0.5 dB step. 00000000: +24.0 dB 00000001: +23.5 dB … 00101111: +0.5 dB 00110000: 0.0 dB 00110001: –0.5 dB ... 11111110: –103 dB 11111111: Mute

13.1.55 Register 62 (0x3E)

Figure 148. Register 62 (0x3E)

7	6	5	4	3	2	1	0
VOLR
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 88. Register 62 (0x3E) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	VOLR	R/W	00110000	Right Digital Volume – These bits control the right channel digital volume. The digital volume is 24 dB to –103 dB in –0.5 dB step. 00000000: +24.0 dB 00000001: +23.5 dB … 00101111: +0.5 dB 00110000: 0.0 dB 00110001: –0.5 dB ... 11111110: –103 dB 11111111: Mute

13.1.56 Register 63 (0x3F)

Figure 149. Register 63 (0x3F)

7	6	5	4	3	2	1	0
VNDF		VNDS		VNUF		VNUS
R/W		R/W		R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 89. Register 63 (0x3F) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	VNDF	R/W	0	Digital Volume Normal Ramp Down Frequency – These bits control the frequency of the digital volume updates when the volume is ramping down. The setting here is applied to soft mute request, asserted by XSMUTE pin or P0-R3. 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly set the volume to zero (Instant mute)
5-4	VNDS	R/W	1	Digital Volume Normal Ramp Down Step – These bits control the step of the digital volume updates when the volume is ramping down. The setting here is applied to soft mute request, asserted by XSMUTE pin or P0-R3. 00: Decrement by 4 dB for each update 01: Decrement by 2 dB for each update 10: Decrement by 1 dB for each update 11: Decrement by 0.5 dB for each update
3-2	VNUF	R/W	0	Digital Volume Normal Ramp Up Frequency – These bits control the frequency of the digital volume updates when the volume is ramping up. The setting here is applied to soft unmute request, asserted by XSMUTE pin or P0-R3. 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly restore the volume (Instant unmute)
1-0	VNUS	R/W	1	Digital Volume Normal Ramp Up Step – These bits control the step of the digital volume updates when the volume is ramping up. The setting here is applied to soft unmute request, asserted by XSMUTE pin or P0-R3. 00: Increment by 4 dB for each update 01: Increment by 2 dB for each update 10: Increment by 1 dB for each update 11: Increment by 0.5 dB for each update

13.1.57 Register 64 (0x40)

Figure 150. Register 64 (0x40)

7	6	5	4	3	2	1	0
VEDF		VEDS		Reserved
R/W		R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 90. Register 64 (0x40) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	VEDF	R/W	0	Digital Volume Emergency Ramp Down Frequency – These bits control the frequency of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute. 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly set the volume to zero (Instant mute)
5-4	VEDS	R/W	1	Digital Volume Emergency Ramp Down Step – These bits control the step of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute. 00: Decrement by 4 dB for each update 01: Decrement by 2 dB for each update 10: Decrement by 1 dB for each update 11: Decrement by 0.5 dB for each update
3-0	Reserved	R/W		Reserved

13.1.58 Register 65 (0x41)

Figure 151. Register 65 (0x41)

7	6	5	4	3	2	1	0
Reserved					ACTL	AMLE	AMRE
R/W					R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 91. Register 65 (0x41) Field Descriptions

Bit	Field	Type	Reset	Description
7-3	Reserved	R/W		Reserved
2	ACTL	R/W	1	Auto Mute ControlNOBUS – This bit controls the behavior of the auto mute upon zero sample detection. The time length for zero detection is set with P0-R59. 0: Auto mute left channel and right channel independently. 1: Auto mute left and right channels only when both channels are about to be auto muted.
1	AMLE	R/W	1	Auto Mute Left ChannelNOBUS – This bit enables or disables auto mute on right channel. Note that when right channel auto mute is disabled and the P0-R65, bit 2 is set to 1, the left channel will also never be auto muted. 0: Disable right channel auto mute 1: Enable right channel auto mute
0	AMRE	R/W	1	Auto Mute Right ChannelNOBUS – This bit enables or disables auto mute on left channel. Note that when left channel auto mute is disabled and the P0-R65, bit 2 is set to 1, the right channel will also never be auto muted. 0: Disable left channel auto mute 1: Enable left channel auto mute

13.1.59 Register 66 (0x42)

Figure 152. Register 66 (0x42)

7	6	5	4	3	2	1	0
ADLY
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 92. Register 66 (0x42) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADLY	R/W	00011001	AMUTE Delay – These bits control the delay before the complete digital mute to the assertion of analog mute. This is to allow the non-mute audio samples to completely flow out through analog parts before the assertion of the analog mute. 00000000: No delay 00000001: 1 LRCLK delay 00000010: 2 LRCLK delay … 11111111: 255 LRCLK delay

13.1.60 Register 67 (0x43)

Figure 153. Register 67 (0x43)

7	6	5	4	3	2	1	0
DLPA		DRPA		DLPM		DRPM
R/W		R/W		R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 93. Register 67 (0x43) Field Descriptions

Bit	Field	Type	Description
7-6	DLPA	R/W	Left DAC primary AC dither gain – These bits control the AC dither gain for left channel primary DAC modulator. 00: AC dither gain = 0.125 01: AC dither gain = 0.25
5-4	DRPA	R/W	Right DAC primary AC dither gain – These bits control the AC dither gain for right channel primary DAC modulator. 00: AC dither gain = 0.125 01: AC dither gain = 0.25
3-2	DLPM	R/W	Left DAC primary DEM dither gain – These bits control the dither gain for left channel primary Galton DEM. 00: DEM dither gain = 0.5 01: DEM dither gain = 1.0 Others: Reserved (do not set)
1-0	DRPM	R/W	Right DAC primary DEM dither gain – These bits control the dither gain for right channel primary Galton DEM. 00: DEM dither gain = 0.5 01: DEM dither gain = 1.0 Others: Reserved (do not set)

13.1.61 Register 68 (0x44)

Figure 154. Register 68 (0x44)

7	6	5	4	3	2	1	0
Reserved					DLPD
R/W					R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 94. Register 68 (0x44) Field Descriptions

Bit	Field	Type	Reset	Description
7-3	Reserved	R/W		Reserved
2-0	DLPD	R/W	0	Left DAC primary DC dither – These bits control the DC dither amount to be added to the lower part of the left channel primary DAC modulator. The DC dither is expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input. 00000000000 : No DC dither 00000000001 : 2^-11 × 1/32 FS 00000000010 : 2^-10 × 1/32 FS

13.1.62 Register 69 (0x45)

Figure 155. Register 69 (0x45)

7	6	5	4	3	2	1	0
DLPD
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 95. Register 69 (0x45) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DLPD	R/W	0	Left DAC primary DC dither – These bits control the DC dither amount to be added to the lower part of the left channel primary DAC modulator. The DC dither is expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input. 00000000000 : No DC dither 00000000001 : 2^-11 × 1/32 FS 00000000010 : 2^-10 × 1/32 FS

13.1.63 Register 70 (0x46)

Figure 156. Register 70 (0x46)

7	6	5	4	3	2	1	0
DRPD
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 96. Register 70 (0x46) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DRPD	R/W	0	Right DAC primary DC dither – These bits control the DC dither amount to be added to the lower part of the right channel primary DAC modulator. The DC dither is expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input. 00000000000 : No DC dither 00000000001 : 2^-11 × 1/32 FS 00000000010 : 2^-10 × 1/32 FS

13.1.64 Register 71 (0x47)

Figure 157. Register 71 (0x47)

7	6	5	4	3	2	1	0
DRPD
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 97. Register 71 (0x47) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DRPD	R/W	0	Right DAC primary DC dither – These bits control the DC dither amount to be added to the lower part of the right channel primary DAC modulator. The DC dither is expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input. 00000000000 : No DC dither 00000000001 : 2^-11 × 1/32 FS 00000000010 : 2^-10 × 1/32 FS

13.1.65 Register 72 (0x48)

Figure 158. Register 72 (0x48)

7	6	5	4	3	2	1	0
DLSA		DRSA		DLSM		RSM
R/W		R/W		R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 98. Register 72 (0x48) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	DLSA	R/W	01	Left DAC secondary AC dither gain – These bits control the AC dither gain for left channel secondary DAC. 00: AC dither gain = 0.125 01: AC dither gain = 0.25
5-4	DRSA	R/W	01	Right DAC secondary AC dither gain – These bits control the AC dither gain for right channel secondary DAC modulator. 00: AC dither gain = 0.125 01: AC dither gain = 0.25 10: AC dither gain = 0.5 11: no AC dither
3-2	DLSM	R/W	01	Left DAC secondary DEM dither gain – These bits control the dither gain for left channel secondary Galton DEM. 00: DEM dither gain = 0.5 01: DEM dither gain = 1.0 Others: Reserved (do not set)
1-0	DRSM	R/W	01	Right DAC secondary DEM dither gain – These bits control the dither gain for right channel secondary Galton DEM. 00: DEM dither gain = 0.5 01: DEM dither gain = 1.0 Others: Reserved (do not set)

13.1.66 Register 73 (0x49)

Figure 159. Register 73 (0x49)

7	6	5	4	3	2	1	0
DLSD
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 99. Register 73 (0x49) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DLSD	R/W	0	Left DAC secondary DC dither – These bits control the DC dither amount to be added to the lower part of the left channel secondary DAC modulator. The DC dither is expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input. 00000000000 : No DC dither 00000000001 : 2^–11 × 1/32 FS 00000000010 : 2^–10 × 1/32 FS

13.1.67 Register 74 (0x4A)

Figure 160. Register 74 (0x4A)

7	6	5	4	3	2	1	0
DLSD
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 100. Register 74 (0x4A) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DLSD	R/W	0	Left DAC secondary DC dither – These bits control the DC dither amount to be added to the lower part of the left channel secondary DAC modulator. The DC dither is expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input. 00000000000 : No DC dither 00000000001 : 2^–11 × 1/32 FS 00000000010 : 2^–10 × 1/32 FS

13.1.68 Register 75 (0x4B)

Figure 161. Register 75 (0x4B)

7	6	5	4	3	2	1	0
DRSD
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 101. Register 75 (0x4B) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DRSD	R/W	00000000	Right DAC secondary DC dither – These bits control the DC dither amount to be added to the lower part of the right channel secondary DAC modulator. The DC dither is expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input. 00000000000 : No DC dither 00000000001 : 2^–11 × 1/32 FS 00000000010 : 2^–10 × 1/32 FS

13.1.69 Register 76 (0x4C)

Figure 162. Register 76 (0x4C)

7	6	5	4	3	2	1	0
DRSD
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 102. Register 76 (0x4C) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DRSD	R/W	00000000	Right DAC secondary DC dither – These bits control the DC dither amount to be added to the lower part of the right channel secondary DAC modulator. The DC dither is expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input. 00000000000 : No DC dither 00000000001 : 2^–11 × 1/32 FS 00000000010 : 2^–10 × 1/32 FS

13.1.70 Register 78 (0x4E)

Figure 163. Register 78 (0x4E)

7	6	5	4	3	2	1	0
OLOF
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 103. Register 78 (0x4E) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	OLOF	R/W	00000000	Left OFSCAL offset – These bits controls the amount of manual DC offset to be added to the left channel DAC output. The additional offset would be approximately the negative of the decimal value of this register divided by 4 in mV. 01111111 : –31.75 mV 01111110 : –31.50 mV … 00000010 : –0.50 mV 00000001 : –0.25 mV 00000000 : 0.0 mV 11111111 : +0.25 mV 11111110 : +0.50 mV … 10000000 : +32.0 mV

13.1.71 Register 79 (0x4F)

Figure 164. Register 79 (0x4F)

7	6	5	4	3	2	1	0
OROF
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 104. Register 79 (0x4F) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	OROF	R/W	0	Right OFSCAL offset – These bits controls the amount of manual DC offset to be added to the right channel DAC output. The additional offset would be approximately the negative of the decimal value of this register divided by 4 in mV. 01111111 : –31.75 mV 01111110 : –31.50 mV … 00000010 : –0.50 mV 00000001 : –0.25 mV 00000000 : 0.0 mV 11111111 : +0.25 mV 11111110 : +0.50 mV … 10000000 : +32.0 mV

13.1.72 Register 80 (0x50)

Figure 165. Register 80 (0x50)

7	6	5	4	3	2	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 105. Register 80 (0x50) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.1.73 Register 81 (0x51)

Figure 166. Register 81 (0x51)

7	6	5	4	3	2	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 106. Register 81 (0x51) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.1.74 Register 82 (0x52)

Figure 167. Register 82 (0x52)

7	6	5	4	3	2	1	0
Reserved			G1SL
R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 107. Register 82 (0x52) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W		Reserved

13.1.75 Register 83 (0x53)

Figure 168. Register 83 (0x53)

7	6	5	4	3	2	1	0
Reserved			G0SL
R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 108. Register 83 (0x53) Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W		Reserved
4-0	G0SL	R/W	0	GPIO0 Output Selection – These bits select the signal to output to GPIO0. To actually output the selected signal, the GPIO0 must be set to output mode at P0-R8. 0110: Clock invalid flag (clock error or clock changing or clock missing) 0111: Serial audio interface data output (SDOUT) 1000: Analog mute flag for left channel (low active) 1001: Analog mute flag for right channel (low active) 1010: PLL lock flag 1011: Charge pump clock 1100: Reserved 1101: Reserved 1110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD 1111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD INTERNAL 1100: Short detection flag for left channel 1101: Short detection flag for right channel 10000: PLL clock/4 10001: Oscillator clock/4 10010: Impedance sense flag for left channel 10011: Impedance sense flag for right channel 10100: Internal UVP flag, becomes low when VDD falls below roughly 2.7V 10101: Offset calibration flag, asserted when the system is offset calibrating itself. 10110: Clock error flag 10111: Clock changing flag 11000: Clock missing flag 11001: Clock halt detection flag 11010: DSP boot done flag 11011: Charge pump voltage output valid flag (low active) Others: N/A (zero)

13.1.76 Register 84 (0x54)

Figure 169. Register 84 (0x54)

7	6	5	4	3	2	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 109. Register 84 (0x54) Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.1.77 Register 85 (0x55)

Figure 170. Register 85 (0x55)

7	6	5	4	3	2	1	0
Reserved			G2SL
R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 110. Register 85 (0x55) Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W	0	Reserved
4-0	G2SL	R/W	0	GPIO2 Output Selection – These bits select the signal to output to GPIO2. To actually output the selected signal, the GPIO2 must be set to output mode at P0-R8. 0000: off (low) 0001: DSP GPIO2 output 0010: Register GPIO2 output (P0-R86, bit 5) 0011: Auto mute flag (asserted when both L and R channels are auto muted) 0100: Auto mute flag for left channel 0101: Auto mute flag for right channel 0110: Clock invalid flag (clock error or clock changing or clock missing) 0111: Serial audio interface data output (SDOUT) 1000: Analog mute flag for left channel (low active) 1001: Analog mute flag for right channel (low active) 1010: PLL lock flag 1011: Charge pump clock 1100: Reserved 1101: Reserved 1110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD 1111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD INTERNAL 1100: Short detection flag for left channel 1101: Short detection flag for right channel 10000: PLL clock/4 10001: Oscillator clock/4 10010: Impedance sense flag for left channel 10011: Impedance sense flag for right channel 10100: Internal UVP flag, becomes low when VDD falls below roughly 2.7V 10101: Offset calibration flag, asserted when the system is offset calibrating itself. 10110: Clock error flag 10111: Clock changing flag 11000: Clock missing flag 11001: Clock halt detection flag 11010: DSP boot done flag 11011: Charge pump voltage output valid flag (low active) Others: N/A (zero)

13.1.78 Register 86 (0x56)

Figure 171. Register 86 (0x56)

7	6	5	4	3	2	1	0
Reserved		GOUT2	MUTE	GOUT0	Reserved	Reserved
R/W		R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 111. Register 86 (0x56) Register Field Descriptions

Bit	Field	Type	Description
7-6	Reserved	R/W	Reserved
5	GOUT2	R/W	GPIO Output Control – This bit controls the GPIO2 output when the selection at P0-R85 is set to 0010 (register output) 0: Output low 1: Output high
4	MUTE	R/W	This bit controls the MUTE output when the selection at P0-R84 is set to 0010 (register output). 0: Output low 1: Output high
3	GOUT0	R/W	This bit controls the GPIO0 output when the selection at P0-R83 is set to 0010 (register output) 0: Output low 1: Output high
2-0	Reserved	R/W	Reserved

13.1.79 Register 87 (0x57)

Figure 172. Register 87 (0x57)

7	6	5	4	3	2	1	0
Reserved		GINV2	MUTE	GINV0	Reserved	Reserved
R/W		R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 112. Register 87 (0x57) Field Descriptions

Bit	Field	Type	Description
7-6	Reserved	R/W	Reserved
5	GINV2	R/W	GPIO Output Inversion – This bit controls the polarity of GPIO2 output. When set to 1, the output will be inverted for any signal being selected. 0: Non-inverted 1: Inverted
4	MUTE	R/W	This bit controls the polarity of MUTE output. When set to 1, the output will be inverted for any signal being selected. 0: Non-inverted 1: Inverted
3	GINV0	R/W	This bit controls the polarity of GPIO0 output. When set to 1, the output will be inverted for any signal being selected. 0: Non-inverted 1: Inverted
2-0	Reserved	R/W	Reserved

13.1.80 Register 88 (0x58)

Figure 173. Register 88 (0x58)

7	6	5	4	3	2	1	0
DIEI
R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 113. Register 88 (0x58) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DIEI	RO	0x84	Die ID, Device ID = 0x84

13.1.81 Register 89 (0x59)

Figure 174. Register 89 (0x59)

7	6	5	4	3	2	1	0
Reserved		VSTL	VENTL	Reserved		VSTR	VENR
R/W		R	R	R/W		R	R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 114. Register 89 (0x59) Field Descriptions

Bit	Field	Type	Description
7-6	Reserved	R/W	Reserved
5	VSTL	R	Left Digital Volume Status – This bit indicates the status of the left channel digital volume. 0: Digital volume is not changing 1: Digital volume is changing
4	VENTL	R	Left Digital Volume Complete Flag – This bit indicates whether the left channel digital volume has reached its target volume. 0: The digital volume has not reached the target volume 1: The digital volume has reached the target volume
3-2	Reserved	R/W	Reserved
1	VSTR	R	Right Digital Volume Status – This bit indicates the status of the right channel digital volume. 0: Digital volume is not changing 1: Digital volume is changing
0	VENR	R	Right Digital Volume Complete Flag – This bit indicates whether the right channel digital volume has reached its target volume. 0: The digital volume has not reached the target volume 1: The digital volume has reached the target volume

13.1.82 Register 91 (0x5B)

Figure 175. Register 91 (0x5B)

7	6	5	4	3	2	1	0
Reserved	DTFS			DTSR
R/W	R			R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 115. Register 91 (0x5B) Field Descriptions

Bit	Field	Type	Description
7	Reserved	R/W	Reserved
6-4	DTFS	R	Detected FS – These bits indicate the currently detected audio sampling rate. 000: Error (Out of valid range) 001: 8 kHz 010: 16 kHz 011: 32-48 kHz 100: 88.2-96 kHz 101: 176.4-192 kHz 110: 384 kHz
3-0	DTSR	R	Detected MCLK Ratio – These bits indicate the currently detected MCLK ratio. Note that even if the MCLK ratio is not indicated as error, clock error might still be flagged due to incompatible combination with the sampling rate. Specifically the MCLK ratio must be high enough to allow enough DSP cycles for minimal audio processing when PLL is disabled. The absolute MCLK frequency must also be lower than 50 MHz. 0000: Ratio error (The MCLK ratio is not allowed) 0001: MCLK = 32 FS 0010: MCLK = 48 FS 0011: MCLK = 64 FS 0100: MCLK = 128 FS 0101: MCLK = 192 FS 0110: MCLK = 256 FS 0111: MCLK = 384 FS 1000: MCLK = 512 FS 1001: MCLK = 768 FS 1010: MCLK = 1024 FS 1011: MCLK = 1152 FS 1100: MCLK = 1536 FS 1101: MCLK = 2048 FS 1110: MCLK = 3072 FS

13.1.83 Register 92 (0x5C)

Figure 176. Register 92 (0x5C)

7	6	5	4	3	2	1	0
Reserved						DTBR
R/W						R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 116. Register 92 (0x5C) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W	0	Reserved
1	DTBR	R	0	Detected SCLK Ratio (MSB)

13.1.84 Register 93 (0x5D)

Figure 177. Register 93 (0x5D)

7	6	5	4	3	2	1	0
DTBR	Reserved
R	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 117. Register 93 (0x5D) Field Descriptions

Bit	Field	Type	Reset	Description
7	DTBR	R		Detected SCLK Ratio (LSB) – These bits indicate the currently detected SCLK ratio, i.e. the number of SCLK clocks in one audio frame. Note that for extreme case of SCLK = 1 FS (which is not usable anyway), the detected ratio will be unreliable
6-0	Reserved	R/W	0	Reserved

13.1.85 Register 94 (0x5E)

Figure 178. Register 94 (0x5E)

7	6	5	4	3	2	1	0
Reserved	CDST6	CDST5	CDST4	CDST3	CDST2	CDST1	CDST0
R/W	R	R	R	R	R	R	R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 118. Register 94 (0x5E) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W	0	Reserved
6	CDST6	R		Clock Detector Status – This bit indicates whether the MCLK clock is present or not. 0: MCLK is present 1: MCLK is missing (halted)
5	CDST5	R		This bit indicates whether the PLL is locked or not. The PLL will be reported as unlocked when it is disabled. 0: PLL is locked 1: PLL is unlocked
4	CDST4	R		This bit indicates whether the both LRCLK and SCLK are missing (tied low) or not. 0: LRCLK and/or SCLK is present 1: LRCLK and SCLK are missing
3	CDST3	R		This bit indicates whether the combination of current sampling rate and MCLK ratio is valid for clock auto set. 0: The combination of FS/MCLK ratio is valid 1: Error (clock auto set is not possible)
2	CDST2	R		This bit indicates whether the MCLK is valid or not. The MCLK ratio must be detectable to be valid. There is a limitation with this flag, that is, when the low period of LRCLK is less than or equal to five SCLKs, this flag will be asserted (MCLK invalid reported). 0: MCLK is valid 1: MCLK is invalid
1	CDST1	R		This bit indicates whether the SCLK is valid or not. The SCLK ratio must be stable and in the range of 32-256FS to be valid. 0: SCLK is valid 1: SCLK is invalid
0	CDST0	R		This bit indicated whether the audio sampling rate is valid or not. The sampling rate must be detectable to be valid. There is a limitation with this flag, that is when this flag is asserted and P0-R37 is set to ignore all asserted error flags such that the DAC recovers, this flag will be de-asserted (sampling rate invalid not reported anymore). 0: Sampling rate is valid 1: Sampling rate is invalid

13.1.86 Register 95 (0x5F)

Figure 179. Register 95 (0x5F)

7	6	5	4	3	2	1	0
Reserved			LTSH	Reserved	CKMF	CSRF	CERF
R/W			R	R/W	R	R	R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 119. Register 95 (0x5F) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W	0	Reserved
4	LTSH	R		Latched Clock Halt – This bit indicates whether MCLK halt has occurred. The bit is cleared when read. 0: MCLK halt has not occurred 1: MCLK halt has occurred since last read
3	Reserved	R/W	0	Reserved
2	CKMF	R		Clock Missing – This bit indicates whether the LRCLK and SCLK are missing (tied low). 0: LRCLK and/or SCLK is present 1: LRCLK and SCLK are missing
1	CSRF	R		Clock Resync Request – This bit indicates whether the clock resynchronization is in progress. 0: Not resynchronizing 1: Clock resynchronization is in progress
0	CERF	R		Clock Error – This bit indicates whether a clock error has occurred. The bit is cleared when read 0: Clock error has not occurred 1: Clock error has occurred.

13.1.87 Register 96 (0x60)

Figure 180. Register 96 (0x60)

7	6	5	4	3	2	1	0
Reserved	PDPM
R/W	R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 120. Register 96 (0x60) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W	0	Reserved
6-0	PDPM	RO		PLL P Monitor – These bits indicate the actually used value for PLL divider P. The actual value is the auto set one when clock auto set is active and register set one when clock auto set is disabled. 0000000: P = 1 0000001: P = 2 ... 1111111: P = 128

13.1.88 Register 97 (0x61)

Figure 181. Register 97 (0x61)

7	6	5	4	3	2	1	0
Reserved		PDJM
R/W		R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 121. Register 97 (0x61) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R/W	0	Reserved
5-0	PDJM	R		PLL J Monitor – These bits indicate the actually used value for PLL multiplication factor J of the overall J.D × R. The actual value is the auto set one when clock auto set is active and register set one when clock auto set is disabled. 000000: Error 000001: J = 1 000010: J = 2 ... 111111: J = 63

13.1.89 Register 98 (0x62)

Figure 182. Register 98 (0x62)

7	6	5	4	3	2	1	0
Reserved		PDDM
R/W		R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 122. Register 98 (0x62) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R/W	0	Reserved
5-0	PDDM	R		PLL D Monitor (MSB) – These bits indicate the actually used value for PLL multiplication factor D of the overall J.D × R. The actual value is the auto set one when clock auto set is active and register set one when clock auto set is disabled. 0 (in decimal): D=0000 1 (in decimal): D=0001 .... 9999 (in decimal): D=9999 Others: Error

13.1.90 Register 99 (0x63)

Figure 183. Register 99 (0x63)

7	6	5	4	3	2	1	0
Reserved		PDDM
R/W		R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 123. Register 99 (0x63) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R/W	0	Reserved
5	PDDM	R		PLL D Monitor (LSB) – These bits indicate the actually used value for PLL multiplication factor D of the overall J.D × R. The actual value is the auto set one when clock auto set is active and register set one when clock auto set is disabled. 0 (in decimal): D=0000 1 (in decimal): D=0001 .... 9999 (in decimal): D=9999 Others: Error

13.1.91 Register 100 (0x64)

Figure 184. Register 100 (0x64)

7	6	5	4	3	2	1	0
Reserved				PDRM
R/W				R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 124. Register 100 (0x64)Field Descriptions

Bit	Field	Type	Reset	Description
7-4	Reserved	R/W	0	Reserved
3-0	PDRM	R		PLL R Monitor – These bits indicate the actually used value for PLL multiplication factor R of the overall J.D × R. The actual value is the auto set one when clock auto set is active and register set one when clock auto set is disabled. 0000: R = 1 0001: R = 2 ... 1111: R = 16

13.1.92 Register 101 (0x65)

Figure 185. Register 101 (0x65)

7	6	5	4	3	2	1	0
Reserved	DDSM
R/W	R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 125. Register 101 (0x65) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W	0	Reserved
6-0	DDSM	R		DSP clock divider monitor – These bits indicate the actually used value of the DSP clock divider ratio. The actual value is the auto set one when clock auto set is active and register set one when clock auto set is disabled. 0000000: Divide by 1 0000001: Divide by 2 ... 1111111: Divide by 128

13.1.93 Register 102 (0x66)

Figure 186. Register 102 (0x66)

7	6	5	4	3	2	1	0
Reserved	DDAM
R/W	R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 126. Register 102 (0x66) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W	0	Reserved
6-0	DDAM	R		DAC clock divider monitor – These bits indicate the actually used value of the DAC clock divider ratio. The actual value is the auto set one when clock auto set is active and register set one when clock auto set is disabled. 0000000: Divide by 1 0000001: Divide by 2 ... 1111111: Divide by 128

13.1.94 Register 103 (0x67)

Figure 187. Register 103 (0x67)

7	6	5	4	3	2	1	0
Reserved	DCPM
R/W	R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 127. Register 103 (0x67) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W	0	Reserved
6-0	DCPM	R		NCP clock divider monitor – These bits indicate the actually used value of the CP clock divider ratio. The actual value is the auto set one when clock auto set is active and register set one when clock auto set is disabled. 0000000: Divide by 1 0000001: Divide by 2 ... 1111111: Divide by 128

13.1.95 Register 104 (0x68)

Figure 188. Register 104 (0x68)

7	6	5	4	3	2	1	0
Reserved	DOSM
R/W	R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 128. Register 104 (0x68) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W	0	Reserved
6-0	DOSM	R		OSR clock divider monitor – These bits indicate the actually used value of the OSR clock divider ratio. The actual value is the auto set one when clock auto set is active and register set one when clock auto set is disabled. 0000000: Divide by 1 0000001: Divide by 2 ... 1111111: Divide by 128

13.1.96 Register 105 (0x69)

Figure 189. Register 105 (0x69)

7	6	5	4	3	2	1	0
Reserved			PENM	Reserved	PRFM
R/W			R	R/W	R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 129. Register 105 (0x69) Field Descriptions

Bit	Field	Type	Description
7-5	Reserved	R/W	Reserved
4	PENM	R	PLL enable monitor – This bit indicates whether the PLL is currently enabled. 0: PLL is disabled 1: PLL is enabled
3	Reserved	R/W	Reserved
2-0	PRFM	R	PLL Reference Monitor – These bits indicate the actual source for the PLL. The source is auto set when clock auto set is active and register set when clock auto set is disabled. 000: MCLK 001: SCLK 010: OSC 011: GPIO Others: Reserved (mute)

13.1.97 Register 106 (0x6A)

Figure 190. Register 106 (0x6A)

7	6	5	4	3	2	1	0
CPPM	RFPM	LDPM	LBPM	LCPM	LOPM	ROPM	DAPM
R	R	R	R	R	R	R	R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 130. Register 106 (0x6A) Field Descriptions

Bit	Field	Type	Description
7	CPPM	R	CP PWRDN monitor – This bit is a monitor for CP powerdown status. 0: Powered down 1: Active
6	RFPM	R	REF PWRDN monitor – This bit is a monitor for analog reference powerdown status. 0: Powered down 1: Active
5	LDPM	R	Line Driver PWRDN monitor – This bit is a monitor for line driver powerdown status. 0: Powered down 1: Active
4	LBPM	R	Line Bias PWRDN monitor – This bit is a monitor for line bias powerdown status. 0: Powered down 1: Active
3	LCPM	R	Line CMFB2 PWRDN monitor – This bit is a monitor for line common feedback powerdown status. 0: Powered down 1: Active
2	LOPM	R	L Output Stage PWRDN monitor – This bit is a monitor for left channel output stage powerdown status. 0: Powered down 1: Active
1	ROPM	R	R Output Stage PWRDN monitor – This bit is a monitor for right channel output stage powerdown status.. 0: Powered down 1: Active
0	DAPM	R	DAC PWRDN monitor – This bit is a monitor for DAC powerdown status. 0: Powered down 1: Active

13.1.98 Register 107 (0x6B)

Figure 191. Register 107 (0x6B)

7	6	5	4	3	2	1	0
OFPM	SSPM	ISPM	IWPM	LSPM	RSPM	DSRM	DERM
R	R	R	R	R	R	R	R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 131. Register 107 (0x6B) Field Descriptions

Bit	Field	Type	Description
7	OFPM	R	OFSCOMP PWRDN monitor – This bit is a monitor for offset compensator powerdown status. 0: Powered down 1: Active
6	SSPM	R	Short Protection PWRDN monitor – This bit is a monitor for short protector powerdown status. 0: Powered down 1: Active
5	ISPM	R	IMP sense PWRDN monitor – This bit is a monitor for impedance sensor powerdown status. 0: Powered down 1: Active
4	IWPM	R	IMP whole PWRDN monitor – This bit is a monitor for whole impedance sensor circuitry powerdown status. 0: Powered down 1: Active
3	LSPM	R	L Short Protection RST monitor – This bit is a monitor for left channel short protector reset status. 0: Reset 1: Active
2	RSPM	R	R Short Protection RST monitor – This bit is a monitor for right channel short protector reset status. 0: Reset 1: Active
1	DSRM	R	DSM RST monitor – This bit is a monitor for DAC modulator reset status. 0: Reset 1: Active
0	DERM	R	DEM RST monitor – This bit is a monitor for DAC DEM reset status. 0: Reset 1: Active

13.1.99 Register 108 (0x6C)

Figure 192. Register 108 (0x6C)

7	6	5	4	3	2	1	0
Reserved		ADLM	ADRM	Reserved		AMLM	AMRM
R/W		R	R	R/W		R	R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 132. Register 108 (0x6C) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R/W	0	Reserved
5	ADLM	R		AMUTE dummy left monitor – This bit is a monitor for left channel dummy output analog mute status. 0: Mute 1: Unmute
4	ADRM	R		AMUTE dummy right monitor – This bit is a monitor for right channel dummy output analog mute status. 0: Mute 1: Unmute
3-2	Reserved	R/W	0	Reserved
1	AMLM	R		Left Analog Mute Monitor – This bit is a monitor for left channel analog mute status. 0: Mute 1: Unmute
0	AMRM	R		Right Analog Mute Monitor – This bit is a monitor for right channel analog mute status. 0: Mute 1: Unmute

13.1.100 Register 109 (0x6D)

Figure 193. Register 109 (0x6D)

7	6	5	4	3	2	1	0
Reserved			SDTM	Reserved			SHTM
R/W			R	R/W			R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 133. Register 109 (0x6D) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W	0	Reserved
4	SDTM	R		Short detect monitor – This bit indicates whether line output short is occuring. 0: Normal (No short) 1: Line output is being shorted
3-1	Reserved	R/W	0	Reserved
0	SHTM	R		Short detected monitor – This bit indicates whether line output short has occurred since last read. This bit is sticky and is cleared when read. 0: No short 1: Line output short occurred

13.1.101 Register 110 (0x6E)

Figure 194. Register 110 (0x6E)

7	6	5	4	3	2	1	0
DLCM
R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 134. Register 110 (0x6E) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DLCM	R		Left DIFF control monitor – These bits indicate the final control value of the left channel differential offset compensator. The value approximates the magnitude of the original offset before calibration. 0000000: 0 mV 0000001: 0.25 mV 0000010: 0.50 mV 0000011: 0.75 mV … 1111111: 63.75 mV

13.1.102 Register 111 (0x6F)

Figure 195. Register 111 (0x6F)

7	6	5	4	3	2	1	0
DRCM
R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 135. Register 111 (0x6F) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DRCM	R		Right DIFF control monitor – These bits indicate the final control value of the right channel differential offset compensator. The value approximates the magnitude of the original offset before calibration. 0000000: 0 mV 0000001: 0.25 mV 0000010: 0.50 mV 0000011: 0.75 mV … 1111111: 63.75 mV

13.1.103 Register 112 (0x70)

Figure 196. Register 112 (0x70)

7	6	5	4	3	2	1	0
DLCS	Reserved		CLCM
R	R/W		R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 136. Register 112 (0x70) Field Descriptions

Bit	Field	Type	Reset	Description
7	DLCS	R		Left DIFF control sign – This bit indicates the polarity of DC offset at left channel before calibration (the magnitude is indicated in R0/P110). 0: Negative 1: Positive
6-5	Reserved	R/W	0	Reserved
4-0	CLCM	R		Left CMFB control monitor – These bits indicate the final control value of the left channel common feedback offset compensator. The value approximates the magnitude of the original offset before calibration. 00000: 0 mV 00001: 0.25 mV 00010: 0.50 mV … 11111: 7.75 mV

13.1.104 Register 113 (0x71)

Figure 197. Register 113 (0x71)

7	6	5	4	3	2	1	0
DRCS	Reserved		CRCM
R	R/W		R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 137. Register 113 (0x71) Field Descriptions

Bit	Field	Type	Reset	Description
7	DRCS	R		Right DIFF control sign – This bit indicates the polarity of DC offset at right channel before calibration (the magnitude is indicated in R0-P111) 0: Negative 1: Positive
6-5	Reserved	R/W	0	Reserved
4-0	CRCM	R		Right CMFB control monitor – These bits indicate the final control value of the right channel common feedback offset compensator. The value approximates the magnitude of the original offset before calibration. 00000: 0 mV 00001: 0.25 mV 00010: 0.50 mV … 11111: 7.75 mV

13.1.105 Register 114 (0x72)

Figure 198. Register 114 (0x72)

7	6	5	4	3	2	1	0
Reserved						MTST
R/W						R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 138. Register 114 (0x72) Field Descriptions

Bit	Field	Type	Reset	Description
7-2	Reserved	R/W	0	Reserved
1-0	MTST	R		MUTE status – These bits indicate the output of the XSMUTE level decoder for monitoring purpose. 11: 0.7 VDD ≤ XSMUTE 01: 0.3 VDD ≤ XSMUTE < 0.7 VDD 00: 0.3 VDD > XSMUTE

13.1.106 Register 115 (0x73)

Figure 199. Register 115 (0x73)

7	6	5	4	3	2	1	0
Reserved					FSMM
R/W					R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 139. Register 115 (0x73) Field Descriptions

Bit

Field

Type

Reset

Description

7-3

Reserved

R/W

Reserved

2-0

FSMM

FS Speed Mode Monitor – These bits indicate the actual FS operation mode being used. The actual value is the auto set one when clock auto set is active and register set one when clock auto set is disabled.

In Auto set,
000: error
001: 8 kHz
010: 16 kHz
011: 32-48 kHz
100: 88.2-96 kHz
101: 176.4-192 kHz
110: 384 kHz
111: reserved

In register set mode,
000: reserved
001: 8 kHz
010: 16 kHz
011: 48 kHz
100: 88.2-96 kHz
101: 176.4-192 kHz
110: 384 kHz
111: 32 kHz

13.1.107 Register 118 (0x76)

Figure 200. Register 118 (0x76)

7	6	5	4	3	2	1	0
BOTM	Reserved			PSTM
R	R/W			R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 140. Register 118 (0x76) Field Descriptions

Bit	Field	Type	Description
7	BOTM	R	DSP Boot Done Flag – This bit indicates whether the DSP boot is completed. 0: DSP is booting 1: DSP boot completed
6-4	Reserved	R/W	Reserved
3-0	PSTM	R	Power State – These bits indicate the current power state of the DAC. 000: Powerdown 0001: Wait for CP voltage valid 0010: Common feedback offset calibration 0011: Differential mode offset calibration 0100: Volume ramp up 0101: Run (Playing) 0110: Line output short and Low impedance 0111: Volume ramp down 1000: Standby

13.1.108 Register 119 (0x77)

Figure 201. Register 119 (0x77)

7	6	5	4	3	2	1	0
Reserved		GPIN2	MUTE	GPIN0	Reserved	Reserved	Reserved
R/W		R	R	R	R	R	R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 141. Register 119 (0x77) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R/W	0	Reserved
5	GPIN2	RO		GPIO Input States – This bit indicates the logic level at GPIO2 pin. 0: Low 1: High
4	MUTE	RO		This bit indicates the logic level at MUTE pin. 0: Low 1: High
3	GPIN0	RO		This bit indicates the logic level at GPIO0 pin. 0: Low 1: High
2		RO		N/A 0: Low 1: High
1		RO		N/A 0: Low 1: High
0		RO		N/A 0: Low 1: High

13.1.109 Register 120 (0x78)

Figure 202. Register 120 (0x78)

7	6	5	4	3	2	1	0
Reserved			AMFL	Reserved			AMFR
R/W			R	R/W			R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 142. Register 120 (0x78) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W	0	Reserved
4	AMFL	R		Auto Mute Flag for Left Channel – This bit indicates the auto mute status for left channel. 0: Not auto muted 1: Auto muted
3-1	Reserved	R/W	0	Reserved
0	AMFR	R		Auto Mute Flag for Right Channel – This bit indicates the auto mute status for right channel. 0: Not auto muted 1: Auto muted

13.1.110 Register 121 (0x79)

Figure 203. Register 121 (0x79)

7	6	5	4	3	2	1	0
Reserved			DWAO	Reserved		DAMD
R/W			R/W	R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 143. Register 121 (0x79) Field Descriptions

Bit	Field	Type	Description
7-5	Reserved	R/W	Reserved
4	DWAO	R/W	DWA off – This bit controls the DWA rotation. 0: DWA is active (Rotation active) 1: DWA is disabled (No rotation)
3-2	Reserved	R/W	Reserved
1-0	DAMD	R/W	DAC Mode – This bit controls the DAC mode. 0: Mode1 1: Mode2 INTERNAL (Mode1: Cascaded Galton, Mode2: Cascaded DWA) 10: Non-cascaded Galton 11: Non-cascaded DWA

13.2 Registers - Page 1

13.2.1 Register 1 (0x01)

Figure 204. Register 1 (0x01)

7	6	5	4	3	2	1	0
Reserved			REXT	Reserved			OSEL
R/W			R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 144. Register 1 (0x01) Field Descriptions

Bit	Field	Type	Description
7-5	Reserved	R/W	Reserved
4	REXT	R/W	REF BG Ext - This bit controls what is output from the VCOM pin 0: AVDD divided voltage 1: Bandgap reference voltage
3-1	Reserved	R/W	Reserved
0	OSEL	R/W	Output Amplitude Type - This bit selects the output amplitude type. The clock autoset feature will not work with PLL enabled in VCOM mode. In this case this feature has to be disabled via P0-R37 and the clock dividers must be set manually. 0: VREF mode (Constant output amplitude against AVDD variation) 1: VCOM mode (Output amplitude is proportional to AVDD variation)

13.2.2 Register 2 (0x02)

Figure 205. Register 2 (0x02)

7	6	5	4	3	2	1	0
Reserved			LAGN	Reserved			RAGN
R/W			R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 145. Register 2 (0x02) Field Descriptions

Bit	Field	Type	Description
7-5	Reserved	R/W	Reserved
4	LAGN	R/W	Analog Gain Control for Left Channel - This bit controls the left channel analog gain. 0: 0 dB 1: -6 dB
3-1	Reserved	R/W	Reserved
0	RAGN	R/W	Analog Gain Control for Right Channel - This bit controls the right channel analog gain. 0: 0 dB 1: -6 dB

13.2.3 Register 3 (0x03)

Figure 206. Register 3 (0x03)

7	6	5	4	3	2	1	0
Reserved					CPDY
R/W					R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 146. Register 3 (0x03) Field Descriptions

Bit	Field	Type	Reset	Description
7-3	Reserved	R/W	0	Reserved
2-0	CPDY	R/W	0	CP Delay -These bits control the delay of charge pump clock. 000: 65 ns 001: 90 ns 010: 115 ns 011: 140 ns 100: 165 ns 101: 190 ns 110: 215 ns 111: 240 ns

13.2.4 Register 4 (0x04)

Figure 207. Register 4 (0x04)

7	6	5	4	3	2	1	0
Reserved						OPWR
R/W						R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 147. Register 4 (0x04) Field Descriptions

Bit	Field	Type	Reset	Description
7-2	Reserved	R/W	0	Reserved
1-0	OPWR	R/W	1	Output Power - These bits control the power of output driver. 00: Normal power 01: Increased power 10: More increased power 11: Maximum power

13.2.5 Register 5 (0x05)

Figure 208. Register 5 (0x05)

7	6	5	4	3	2	1	0
Reserved						UEPD	UIPD
R/W						R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 148. Register 5 (0x05) Field Descriptions

Bit	Field	Type	Description
7-2	Reserved	R/W	Reserved
1	UEPD	R/W	External UVP Control - This bit enables or disables detection of power supply drop via XSMUTE pin (External Under Voltage Protection). 0: Enabled 1: Disabled
0	UIPD	R/W	Internal UVP Control - This bit enables or disables internal detection of AVDD voltage drop (Internal Under Voltage Protection). 0: Enabled 1: Disabled

13.2.6 Register 6 (0x06)

Figure 209. Register 6 (0x06)

7	6	5	4	3	2	1	0
Reserved							AMCT
R/W							R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 149. Register 6 (0x06) Field Descriptions

Bit	Field	Type	Reset	Description
7-1	Reserved	R/W	0	Reserved
0	AMCT	R/W	1	Analog Mute Control -This bit enables or disables analog mute following digital mute. 0: Disabled 1: Enabled

13.2.7 Register 7 (0x07)

Figure 210. Register 7 (0x07)

7	6	5	4	3	2	1	0
Reserved			AGBL	Reserved			AGBR
R/W			R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 150. Register 7 (0x07) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W	0	Reserved
4	AGBL	R/W	0	Analog +10% Gain for Left Channel - This bit enables or disables amplitude boost mode for left channel. 0: Normal amplitude 1: +10% (+0.8 dB) boosted amplitude
3-1	Reserved	R/W	0	Reserved
0	AGBR	R/W	1	Analog +10% Gain for Right Channel - This bit enables or disables amplitude boost mode for right channel. 0: Normal amplitude 1: +10% (+0.8 dB) boosted amplitude

13.2.8 Register 8 (0x08)

Figure 211. Register 8 (0x08)

7	6	5	4	3	2	1	0
Reserved			RBGF	Reserved			RCMF
R/W			R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 151. Register 8 (0x08) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W	0	Reserved
4	RBGF	R/W	0	REF BG Fast - This bit controls the bandgap voltage ramp up speed. 0: Normal ramp up, ~50 ms with external capacitance = 1 µF 1: Fast ramp up, ~1 ms with external capacitance = 1 µF
3-1	Reserved	R/W	0	Reserved
0	RCMF	R/W	1	VCOM Reference Ramp Up - This bit controls the VCOM voltage ramp up speed. 0: Normal ramp up, ~600 ms with external capacitance = 1 µF 1: Fast ramp up, ~3 ms with external capacitance = 1 µF

13.2.9 Register 9 (0x09)

Figure 212. Register 9 (0x09)

7	6	5	4	3	2	1	0
Reserved						DEME	VCPD
R/W						R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 152. Register 9 (0x09) Field Descriptions

Bit	Field	Type	Reset	Description
7-2	Reserved	R/W	0	Reserved
1	DEME	R/W	0	VCOM Pin as De-emphasis Control - This bit controls whether to use the DEEMP/VCOM pin as De-emphasis control. 0: Disabled (DEEMP/VCOM is not used to control De-emphasis) 1: Enabled (DEEMP/VCOM is used to control De-emphasis)
0	VCPD	R/W	1	Power down control for VCOM - This bit controls VCOM powerdown switch. 0: VCOM is powered on 1: VCOM is powered down

13.2.10 Register 10 (0x0A)

Figure 213. Register 10 (0x0A)

7	6	5	4	3	2	1	0
Reserved		LBBG		Reserved		LBVC
R/W		R/W		R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 153. Register 10 (0x0A) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R/W	0	Reserved
5-4	LBBG	R/W	1	Line 1st stage bias ctrl<1> at BG mode - Applied when LSB of 0x01 at Page1=0 0: low 1: high
3-2	Reserved	R/W	0	Reserved
1-0	LBVC	R/W	1	Line 1st stage bias ctrl<1> at COM mode - Applied when LSB of 0x01 at Page1=1 0: low 1: high

13.2.11 Register 11 (0x0B)

Figure 214. Register 11 (0x0B)

7	6	5	4	3	2	1	0
Reserved		CBBG		Reserved		CBVC
R/W		R/W		R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 154. Register 11 (0x0B) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R/W	0	Reserved
5-4	CBBG	R/W	1	CMFB bias ctrl<1> at BG mode - Applied when LSB of 0x01 at Page1=0 0: low 1: high
3-2	Reserved	R/W	0	Reserved
1-0	CBVC	R/W	0	CMFB bias ctrl<1> at COM mode - Applied when LSB of 0x01 at Page1=1 0: low 1: high

13.2.12 Register 12 (0x0C)

Figure 215. Register 12 (0x0C)

7	6	5	4	3	2	1	0
Reserved		SSBG		Reserved		SSVC
R/W		R/W		R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 155. Register 12 (0x0C) Field Descriptions

Bit	Field	Type	Description
7-6	Reserved	R/W	Reserved
5-4	SSBG	R/W	Short protection sink ref current ctrl<1> at BG mode - Applied when LSB of 0x01at Page1=0 0: low 1: high
3-2	Reserved	R/W	Reserved
1-0	SSVC	R/W	Short protection sink ref current ctrl<1> at COM mode - Applied when LSB of 0x01 at Page1=1 0: low 1: high

13.2.13 Register 13 (0x0D)

Figure 216. Register 13 (0x0D)

7	6	5	4	3	2	1	0
Reserved		SRBG				SRVC
R/W		R/W				R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 156. Register 13 (0x0D) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R/W	0	Reserved
5	SRBG	R/W	0	Short protection source ref current ctrl<1> at BG mode - Applied when LSB of 0x01 at Page1=0 0: low 1: high
4-2	SRBG	R/W	1
1	SRVC	R/W	0	Short protection source ref current ctrl<1> at COM mode - Applied when LSB of 0x01 at Page1=1 0: low 1: high
0	SRVC	R/W	1

13.2.14 Register 14 (0x0E)

Figure 217. Register 14 (0x0E)

7	6	5	4	3	2	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 157. Register 14 (0x0E) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.2.15 Register 15 (0x0F)

Figure 218. Register 15 (0x0F)

7	6	5	4	3	2	1	0
Reserved							CPCP
R/W							R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 158. Register 15 (0x0F) Field Descriptions

Bit	Field	Type	Reset	Description
7-1	Reserved	R/W	0	Reserved
0	CPCP	R/W	1	NCP clock digital delay control - This bit controls the CP clock phase delay against the DAC clock. 0: 0 degree (no delay) 1: 180 degree delay

13.3 Registers - Page 253

13.3.1 Register 1 (0x01)

Figure 219. Register 1 (0x01)

7	6	5	4	3	2	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 159. Register 1 (0x01) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.2 Register 2 (0x02)

Figure 220. Register 2 (0x02)

7	6	5	4	3	2	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 160. Register 2 (0x02) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.3 Register 3 (0x03)

Figure 221. Register 3 (0x03)

7	6	5	4	3	2	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 161. Register 3 (0x03 Field Descriptions)

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.4 Register 4 (0x04)

Figure 222. Register 4 (0x04)

7	6	5	4	3	2	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 162. Register 4 (0x04) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.5 Register 5 (0x05)

Figure 223. Register 5 (0x05)

7	6	5	4	3	2	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 163. Register 5 (0x05) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.6 Register 6 (0x06)

Figure 224. Register 6 (0x06)

7	6	5	4	3	2	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 164. Register 6 (0x06) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.7 Register 7 (0x07)

Figure 225. Register 7 (0x07)

7	6	5	4	3	2	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 165. Register 7 (0x07) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.8 Register 8 (0x08)

Figure 226. Register 8 (0x08)

7	6	5	4	3	2	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 166. Register 8 (0x8) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.9 Register 9 (0x09)

Figure 227. Register 9 (0x09)

7	6	5	4	3	2	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 167. Register 9 (0x9) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.10 Register 10 (0x0A)

Figure 228. Register 10 (0x0A)

7	6	5	4	3	2	1	0
DRSV	Reserved
R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 168. Register 10 (0xA) Field Descriptions

Bit	Field	Type	Reset	Description
7	DRSV	R/W	0	Dither Reserved - Performance adjustment dither setting when "RESERVED" bond option is selected
6-0	Reserved	R/W	0	Reserved

13.3.11 Register 11 (0x0B)

Figure 229. Register 11 (0x0B)

7	6	5	4	3	2	1	0
D100	Reserved		OFSCAL0	OFSCAL1	OFSCAL2	OFSCAL3	OFSCAL4
R/W	R/W		R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 169. Register 11 (0xB) Field Descriptions

Bit	Field	Type	Description
7	D100	R/W	Dither Reserved - Performance adjustment dither setting when "RESERVED" bond option is selected
6-5	Reserved	R/W	Reserved
4	OFSCAL0	R/W	Ofscal Bypass Filter - Select whether to bypass the front-end filter. 0: Front-end filter used. 1: Front-end filter bypassed.
3	OFSCAL1	R/W	Ofscal Full Span - Select whether to activate front-end filter half period (good for majority type) or full period (good for averaging type). 0: Front-end filter is active last half of control period. 1: Front-end filter is active the whole control period.
2	OFSCAL2	R/W	Ofscal Average Filtering - Select the type of front-end filter. 0: Front-end filter is majority decision type 1: Front-end filter is averaging type
1	OFSCAL3	R/W	Ofscal Disable Fine Calibration - Select whether to do fine calibration. 0: Do 64-step coarse calibration followed by 32-step fine calibration. 1: Do 96-step coarse calibration only (no fine calibration).
0	OFSCAL4	R/W	Ofscal Disable Post Averaging - Select whether to use post-averaging on the integrator output. 0: Final calibration control source is post-averaging result. 1: Final calibration control source is integrator output.

13.3.12 Register 12 (0x0C)

Figure 230. Register 12 (0x0C)

7	6	5	4	3	2	1	0
D105	Reserved
R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 170. Register 12 (0x0C) Field Descriptions

Bit	Field	Type	Reset	Description
7	D105	R/W	0	Dither 105 dB - Performance adjustment dither setting when "105dB" bond option is selected
6-0	Reserved	R/W	0	Reserved

13.3.13 Register 13 (0x0D)

Figure 231. Register 13 (0x0D)

7	6	5	4	3	2	1	0
D110	Reserved
R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 171. Register 13 (0x0D) Field Descriptions

Bit	Field	Type	Reset	Description
7	D110	R/W	0	Dither 115 dB - Performance adjustment dither setting when "110dB" bond option is selected
6-0	Reserved	R/W	0	Reserved

13.3.14 Register 14 (0x0E)

Figure 232. Register 14 (0x0E)

7	6	5	4	3	2	1	0
Reserved			SUMD	Reserved			SUAS
R/W			R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 172. Register 14 (0x0E) Field Descriptions

Bit	Field	Type	Description
7-5	Reserved	R/W	Reserved
4	SUMD	R/W	SpeedUp CLK missing detection
3-1	Reserved	R/W	Reserved
0	SUAS	R/W	SpeedUp Analog Sequence

13.3.15 Register 15 (0x0F)

Figure 233. Register 15 (0x0F)

7	6	5	4	3	2	1	0
Reserved			SDEN	Reserved			DSOC
R/W			R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 173. Register 15 (0x0F) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W	0	Reserved
4	SDEN	R/W	1	Short Detection Enable 0: Short detection enable 1: Short detection disable
3-1	Reserved	R/W	0	Reserved
0	DSOC	R/W	0	Disable Subsequent Offset Cancellation

13.3.16 Register 16 (0x10)

Figure 234. Register 16 (0x10)

7	6	5	4	3	2	1	0
Reserved		SWDA		Reserved			DPOL
R/W		R/W		R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 174. Register 16 (0x10) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved		0	Reserved
5	SDWA	R/W	1	Shuffle DWA of Galton - Shuffle DWA Outputs of Galton DEM 0,3: No shuffle
4	SDWA	R/W	0	1: Shuffle Internally 2: Global Shuffle
3-1	Reserved		0	Reserved
0	DPOL	R/W	0	Select DC dither polarity for the secandary DAC. Select DC dither polarity +4.0% or -4.0% for the secondary DAC.

13.3.17 Register 17 (0x11)

Figure 235. Register 17 (0x11)

7	6	5	4	3	2	1	0
DLSC	Reserved			DRSC	Reserved
R/W	R/W			R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 175. Register 17 (0x11) Field Descriptions

Bit	Field	Type	Description
7	DLSC	R/W	Left DAC Primary/Secondary Scale - Secondary to Primary scaling factor for left DAC
6-4	Reserved	R/W	Reserved
3	DRSC	R/W	Right DAC Primary/Secondary Scale - See DAC digital design spec
2-0	Reserved	R/W	Reserved

13.3.18 Register 18 (0x12)

Figure 236. Register 18 (0x12)

7	6	5	4	3	2	1	0
LPA0	LPB1	LPB2	LPB3	RPA0	RPB1	RPB2	RPB3
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 176. Register 18 (0x12) Field Descriptions

Bit	Field	Type	Description
7	LPA0	R/W	Left DAC primary a0 zero - Left DAC primary modulator coeff tweaks. 0: normal 1: zero
6	LPB1	R/W	Left DAC primary b1 zero 0: normal 1: zero
5	LPB2	R/W	Left DAC primary b2 zero 0: normal 1: zero
4	LPB3	R/W	Left DAC primary b3 zero 0: normal 1: zero
3	RPA0	R/W	Right DAC primary a0 zero - Right DAC primary modulator coeff tweaks 0: normal 1: zero
2	RPB1	R/W	Right DAC primary b1 zero 0: normal 1: zero
1	RPB2	R/W	Right DAC primary b2 zero 0: normal 1: zero
0	RPB3	R/W	Right DAC primary b3 zero 0: normal 1: zero

13.3.19 Register 19 (0x13)

Figure 237. Register 19 (0x13)

7	6	5	4	3	2	1	0
LPG1	Reserved	LPUB	Reserved	RPG1	Reserved	RPUB	Reserved
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 177. Register 19 (0x13) Field Descriptions

Bit	Field	Type	Description
7	LPG1	R/W	Left DAC primary g1 gain. Left DAC primary local loop gain
6	Reserved	R/W	Reserved
5	LPUB	R/W	Left DAC primary upper bits. Number of left DAC primary upper bits
4	Reserved	R/W	Reserved
3	RPG1	R/W	Right DAC primary g1 gain. Right DAC primary local loop gain
2	Reserved	R/W	Reserved
1	RPUB	R/W	Right DAC primary upper bits. Number of right DAC primary upper bits
0	Reserved	R/W	Reserved

13.3.20 Register 20 (0x14)

Figure 238. Register 20 (0x14)

7	6	5	4	3	2	1	0
LSA0	LSB1	LSB2	LSB3	RSA0	RSB1	RSB2	RSB3
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 178. Register 20 (0x14) Field Descriptions

Bit	Field	Type	Description
7	LSA0	R/W	Left DAC secondary a0 zero. Left DAC secondary modulator coeff tweaks. 0: normal 1: zero
6	LSB1	R/W	Left DAC secondary b1 zero 0: normal 1: zero
5	LSB2	R/W	Left DAC secondary b2 zero 0: normal 1: zero
4	LSB3	R/W	Left DAC secondary b3 zero 0: normal 1: zero
3	RSA0	R/W	Right DAC secondary a0 zero. Right DAC seconday modulator coeff tweaks. 0: normal 1: zero
2	RSB1	R/W	Right DAC secondary b1 zero 0: normal 1: zero
1	RSB2	R/W	Right DAC secondary b2 zero 0: normal 1: zero
0	RSB3	R/W	Right DAC secondary b3 zero 0: normal 1: zero

13.3.21 Register 21 (0x15)

Figure 239. Register 21 (0x15)

7	6	5	4	3	2	1	0
LSG1	Reserved	LSUB	Reserved	RSG1	Reserved	RSUB	Reserved
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 179. Register 21 (0x15) Field Descriptions

Bit	Field	Type	Description
7	LSG1	R/W	Left DAC secondary g1 gain. Left DAC secondary local loop gain
6	Reserved	R/W	Reserved
5	LSUB	R/W	Left DAC secondary upper bits. Number of left DAC secondary upper bits
4	Reserved	R/W	Reserved
3	RSG1	R/W	Right DAC secondary g1 gain. Right DAC secondary local loop gain
2	Reserved	R/W	Reserved
1	RSUB	R/W	Right DAC secondary upper bits. Number of right DAC secondary upper bits
0	Reserved	R/W	Reserved

13.3.22 Register 2 (0x16)

Figure 240. Register 22 (0x16)

7	6	5	4	3	2	1	0
Reserved						CPHY
R/W						R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 180. Register 22 (0x16) Field Descriptions

Bit	Field	Type	Reset	Description
7-2	Reserved	R/W	0	Reserved
1-0	CPHY	R/W	1	CP Hysterisis - Hysterisis control of VNEG Detector

13.3.23 Register 23 (0x17)

Figure 241. Register 23 (0x17)

7	6	5	4	3	2	1	0
Reserved						CPHY
R/W						R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 181. Register 23 (0x17) Field Descriptions

Bit	Field	Type	Reset	Description
7-2	Reserved	R/W	0	Reserved
1-0	CPHY	R/W	1	CP Hysterisis - Hysterisis control of VNEG Detector

13.3.24 Register 24 (0x18)

Figure 242. Register 24 (0x18)

7	6	5	4	3	2	1	0
Reserved					OT33
R/W					R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 182. Register 24 (0x18) Field Descriptions

Bit	Field	Type	Reset	Description
7-3	Reserved	R/W	0	Reserved
2	OT33	R/W	1	Bias current trimming for internal 3.3V oscillator. Bias current 00-111: ?-?uA
1		R/W	0
0		R/W	0

13.3.25 Register 25 (0x19)

Figure 243. Register 25 (0x19)

7	6	5	4	3	2	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 183. Register 25 (0x19) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.26 Register 26 (0x1A)

Figure 244. Register 26 (0x1A)

7	6	5	4	3	2	1	0
RBTR				RCTR
R/W				R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 184. Register 26 (0x1A) Field Descriptions

Bit	Field	Type	Reset	Description
7	RBTR	R/W	0	REF BTrim. Trimming of bandgap reference voltage.
6		R/W	1
5		R/W	0
4		R/W	0
3-0	RCTR	R/W	0	REF CTrim. Trimming of common voltage dividing AVDD.

13.3.27 Register 27 (0x1B)

Figure 245. Register 27 (0x1B)

7	6	5	4	3	2	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 185. Register 27 (0x1B) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.28 Register 28 (0x1C)

Figure 246. Register 28 (0x1C)

7	6	5	4	3	2	1	0
Reserved			PLLR	Reserved		PTST	PVC1
R/W			R/W	R/W		R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 186. Register 28 (0x1C) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W	0	Reserved
4	PLLR	R/W	1	PLL RST - Reset counter of all divider. 0: Reset 1: Normal operation
3-2	Reserved	R/W	0	Reserved
1	PTST	R/W	0	PLL IREF TEST. IREF test mode enable/disable. 0: normal 1: test mode
0	PVCI	R/W	0	PLL VCIC. 0: Normal operation 1: Brings higher free-running frequency

13.3.29 Register 29 (0x1D)

Figure 247. Register 29 (0x1D)

7	6	5	4	3	2	1	0
PLL IREF
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 187. Register 29 (0x1D) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PLL IREF	R/W	0	Reference current control on test-mode. 00000000-11111111: ?? -??A

13.3.30 Register 30 (0x1E)

Figure 248. Register 30 (0x1E)

7	6	5	4	3	2	1	0
Reserved							PLLT
R/W							R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 188. Register 30 (0x1E) Field Descriptions

Bit	Field	Type	Reset	Description
7-1	Reserved	R/W	0	Reserved
0	PLLT	R/W	0	PLL TEST - Power up/down control for PFD in PLL at test mode. 0: Power up 1: Power down

13.3.31 Register 31 (0x1F)

Figure 249. Register 31 (0x1F)

7	6	5	4	3	2	1	0
Reserved			LSFG	Reserved			LSPD
R/W			R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 189. Register 31 (0x1F) Field Descriptions

Bit	Field	Type	Description
7-5	Reserved	R/W	Reserved
4	LSFG	R/W	LDO_SCPZ - LDO short flag. 0: Short state 1: Not short state
3-1	Reserved	R/W	Reserved
0	LSPD	R/W	LDO SCPD - LDO power down behavior at short condition. 0: LDO is automatically power down if short state detects 1: Disable

13.3.32 Register 32 (0x20)

Figure 250. Register 32 (0x20)

7	6	5	4	3	2	1	0
Reserved						UTM1	UTM2
R/W						R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 190. Register 32 (0x20) Field Descriptions

Bit	Field	Type	Reset	Description
7-2	Reserved	R/W	0	Reserved
1	UTM1	R/W		UVP TEST mode 1 - Change external threshold voltage. 0: VH=0.7xDVDD, VL=0.3xDVDD 1: VH=0.67xDVDD, VL=0.33xDVDD
0	UTM2	R/W	0	UVP TEST mode 2 - Change reference source for internal AVDD detection. 0: Divided LDO_1p8 by resistor 1: Bandgap reference of UVP

13.3.33 Register 33 (0x21)

Figure 251. Register 33 (0x21)

7	6	5	4	3	2	1	0
Reserved				TST1	TST2	TST3	TST4
R/W				R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 191. Register 33 (0x21) Field Descriptions

Bit	Field	Type	Reset	Description
7-4	Reserved	R/W	0	Reserved
3	TST1	R/W	0	Analog test mode 1 - Line first stage load ctrl <0> 0: Disable 1: Enable
2	TST2	R/W	0	Analog test mode 2 - Line first stage load ctrl <1>0: Disable 1: Enable
1	TST3	R/W	1	Analog test mode 3 - Line slew rate ctrl <0> 0: Disable 1: Enable
0	TST4	R/W	1	Analog test mode 4 - Line slew rate ctrl <1> 0: Disable 1: Enable

13.3.34 Register 34 (0x22)

Figure 252. Register 34 (0x22)

7	6	5	4	3	2	1	0
Reserved		RFPO	DLPO	LLPO	BLPO	CLPO	OLPO
R/W		R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 192. Register 34 (0x22) Field Descriptions

Bit	Field	Type	Description
7-6	Reserved	R/W	Reserved
5	RFPO	R/W	REF PWRDN override. Power up/down control for whole bias current. 0: normal 1: override
4	DLPO	R/W	Lch DAC PWRDN override. Power up/down control for Lch current DAC. 0: normal 1: override
3	LLPO	R/W	Lch Line Driver PWRDN override. Power up/down control for Lch line driver 0: normal 1: override
2	BLPO	R/W	Lch Line Bias PWRDN override. Power up/down control for bais block of Lch line driver 0: normal 1: override
1	CLPO	R/W	Lch Line CMFB2 PWRDN override. Power up/down control for CMFB of Lch line driver 0: normal 1: override
0	OLPO	R/W	Lch Output Stage PWRDN override. Power up/down control for output stage of Lch line driver 0: normal 1: override

13.3.35 Register 35 (0x23)

Figure 253. Register 35 (0x23)

7	6	5	4	3	2	1	0
GLPO	ALPO	ULPO	CPPO	FLPO	SLPO	ILPO	WLPO
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 193. Register 35 (0x23) Field Descriptions

Bit	Field	Type	Description
7	GLPO	R/W	Lch Gain control PWRDN override. Power up/down control for Lch gain control 0: normal 1: override
6	ALPO	R/W	Lch AMUTE override. Lch Analog Mute control. 0: normal 1: override
5	ULPO	R/W	Lch AMUTE dummy override. Lch Analog Mute control. 0: normal 1: override
4	CPPO	R/W	CP PWRDN override. Power up/down control for negative charge pump. 0: normal 1: override
3	FLPO	R/W	Lch OFSCOMP PWRDN override. Power up/down control for offset calibration block for Lch line driver. 0: normal 1: override
2	SLPO	R/W	Lch Short Protection PWRDN override. Power up/down control for short protection of Lch line driver. 0: normal 1: override
1	ILPO	R/W	Lch IMP sense PWRDN override. Power up/down control for impedance sensing circuit of Lch line driver. 0: normal 1: override
0	WLPO	R/W	Lch IMP whole PWRDN override. Power up/down control for impedance sensing circuit of Lch line driver at whole analog power down. 0: normal 1: override

13.3.36 Register 36 (0x24)

Figure 254. Register 36 (0x24)

7	6	5	4	3	2	1	0
Reserved		RFPS	DLPS	LLPS	BLPS	CLPS	OLPS
R/W		R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 194. Register 36 (0x24) Field Descriptions

Bit	Field	Type	Description
7-6	Reserved	R/W	Reserved
5	RFPS	R/W	REF PWRDN state. Power up/down control for whole bias current. 0: Power down 1: Power up
4	DLPS	R/W	Lch DAC PWRDN state. Power up/down control for Lch current DAC. 0: Power down 1: Power up
3	LLPS	R/W	Lch Line Driver PWRDN state. Power up/down control for Lch line driver. 0: Power down 1: Power up
2	BLPS	R/W	Lch Line Bias PWRDN state .Power up/down control for bais block of Lch line driver. 0: Power down 1: Power up
1	CLPS	R/W	Lch Line CMFB2 PWRDN state. Power up/down control for CMFB of Lch line driver. 0: Power down 1: Power up
0	OLPS	R/W	Lch Output Stage PWRDN state. Power up/down control for output stage of Lch line driver. 0: Power down 1: Power up

13.3.37 Register 37 (0x25)

Figure 255. Register 37 (0x25)

7	6	5	4	3	2	1	0
GLPS	ALPS	ULPS	CPPS	FLPS	SLPS	ILPS	WLPS
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 195. Register 37 (0x25) Field Descriptions

Bit	Field	Type	Description
7	GLPS	R/W	Lch Gain control PWRDN state. Power up/down control for Lch gain control. 0: Power down 1: Power up
6	ALPS	R/W	Lch AMUTE state. Lch Analog Mute control. 0: Power down 1: Power up
5	ULPS	R/W	Lch AMUTE dummy state. Lch Analog Mute control. 0: Power down 1: Power up
4	CPPS	R/W	CP PWRDN state. Power up/down control for negative charge pump. 0: Power down 1: Power up
3	FLPS	R/W	Lch OFSCOMP PWRDN state. Power up/down control for offset calibration block for Lch line driver. 0: Power down 1: Power up
2	SLPS	R/W	Lch Short Protection PWRDN state. Power up/down control for short protection of Lch line driver. 0: Power down 1: Power up
1	ILPS	R/W	Lch IMP sense PWRDN state. Power up/down control for impedance sensing circuit of Lch line driver. 0: Power down 1: Power up
0	WLPS	R/W	Lch IMP whole PWRDN state. Power up/down control for impedance sensing circuit of Lch line driver at whole analog power down. 0: Power down 1: Power up

13.3.38 Register 38 (0x26)

Figure 256. Register 38 (0x26)

7	6	5	4	3	2	1	0
Reserved			DRPO	LRPO	BRPO	CRPO	ORPO
R/W			R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 196. Register 38 (0x26) Field Descriptions

Bit	Field	Type	Description
7-5	Reserved	R/W	Reserved
4	DRPO	R/W	Rch DAC PWRDN override. Power up/down control for Rch current DAC. 0: normal 1: override
3	LRPO	R/W	Rch Line Driver PWRDN override. Power up/down control for Rch line driver. 0: normal 1: override
2	BRPO	R/W	Rch Line Bias PWRDN override. Power up/down control for bais block of Rch line driver. 0: normal 1: override
1	CRPO	R/W	Rch Line CMFB2 PWRDN override. Power up/down control for CMFB of Rch line driver. 0: normal 1: override
0	ORPO	R/W	Rch Output Stage PWRDN override. Power up/down control for output stage of Rch line driver. 0: normal 1: override

13.3.39 Register 39 (0x27)

Figure 257. Register 39 (0x27)

7	6	5	4	3	2	1	0
GRPO	ARPO	URPO	Reserved	FRPO	SRPO	IRPO	WRPO
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 197. Register 39 (0x27) Field Descriptions

Bit	Field	Type	Description
7	GRPO	R/W	Rch Gain control PWRDN override. Power up/down control for Rch gain control. 0: normal 1: override
6	ARPO	R/W	Rch AMUTE override. Rch Analog Mute control. 0: normal 1: override
5	URPO	R/W	Rch AMUTE dummy override. Rch Analog Mute control. 0: normal 1: override
4	Reserved	R/W	Reserved
3	FRPO	R/W	Rch OFSCOMP PWRDN override. Power up/down control for offset calibration block for Rch line driver. 0: normal 1: override
2	SRPO	R/W	Rch Short Protection PWRDN override. Power up/down control for short protection of Rch line driver. 0: normal 1: override
1	IRPO	R/W	Rch IMP sense PWRDN override. Power up/down control for impedance sensing circuit of Rch line driver. 0: normal 1: override
0	WRPO	R/W	Rch IMP whole PWRDN override. Power up/down control for Rch impedance sensing circuit of Rch line driver at whole analog power down. 0: normal 1: override

13.3.40 Register 40 (0x28)

Figure 258. Register 40 (0x28)

7	6	5	4	3	2	1	0
Reserved			DRPS	LRPS	BRPS	CRPS	ORPS
R/W			R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 198. Register 40 (0x28) Field Descriptions

Bit	Field	Type	Description
7-5	Reserved	R/W	Reserved
4	DRPS	R/W	Rch DAC PWRDN state. Power up/down control for Rch current DAC. 0: Power down 1: Power up
3	LRPS	R/W	Rch Line Driver PWRDN state. Power up/down control for Rch line driver. 0: Power down 1: Power up
2	BRPS	R/W	Rch Line Bias PWRDN state. Power up/down control for bais block of Rch line driver. 0: Power down 1: Power up
1	CRPS	R/W	Rch Line CMFB2 PWRDN state. Power up/down control for CMFB of Rch line driver. 0: Power down 1: Power up
0	ORPS	R/W	Rch Output Stage PWRDN state. Power up/down control for output stage of Rch line driver. 0: Power down 1: Power up

13.3.41 Register 41 (0x29)

Figure 259. Register 41 (0x29)

7	6	5	4	3	2	1	0
GRPS	ARPS	URPS	Reserved	FRPS	SRPS	IRPS	WRPS
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 199. Register 41 (0x29) Field Descriptions

Bit	Field	Type	Description
7	GRPS	R/W	Rch Gain control PWRDN state. Power up/down control for Rch gain control. 0: Power down 1: Power up
6	ARPS	R/W	Rch AMUTE state. Rch Analog Mute control. 0: Power down 1: Power up
5	URPS	R/W	Rch AMUTE dummy state. Rch Analog Mute control. 0: Power down 1: Power up
4	Reserved	R/W	Reserved
3	FRPS	R/W	Rch OFSCOMP PWRDN state. Power up/down control for offset calibration block for Rch line driver. 0: Power down 1: Power up
2	SRPS	R/W	Rch Short Protection PWRDN state. Power up/down control for short protection of Rch line driver. 0: Power down 1: Power up
1	IRPS	R/W	Rch IMP sense PWRDN state. Power up/down control for impedance sensing circuit of Rch line driver. 0: Power down 1: Power up
0	WRPS	R/W	Rch IMP whole PWRDN state. Power up/down control for Rch impedance sensing circuit of Rch line driver at whole analog power down. 0: Power down 1: Power up

13.3.42 Register 42 (0x2A)

Figure 260. Register 42 (0x2A)

7	6	5	4	3	2	1	0
Reserved			CMEN	Reserved			CMSL
R/W			R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 200. Register 42 (0x2A) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W	0	Reserved
4	CMEN	R/W	0	CP operation mode control enable. Enable/Disable for charge pump mode select. 0: Disable 1: Enable
3-1	Reserved	R/W	0	Reserved
0	CMSL	R/W	1	CP operation mode select. Charge pump mode select by register. 0: Normal operation 1: Constant current mode

13.3.43 Register 43 (0x2B)

Figure 261. Register 43 (0x2B)

7	6	5	4	3	2	1	0
Reserved			CHDP	Reserved		CHI4	HDEN
R/W			R/W	R/W		R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 201. Register 43 (0x2B) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W	0	Reserved
4	CHDP	R/W	1	CHD power up/down control. Power up/down control for clock halt detector. 0: Power down 1: Power up
3-2	Reserved	R/W	0	Reserved
1	CHI4	R/W	0	CHD current control override. x4 current control for clock halt detector. 0: Normal operation 1: x4 current operation
0	HDEN	R/W	0	CHD detector enable/disable control. Enable/disable control for clock halt detector. At 'disable', output shows "1". 0: Enable 1: Disable

13.3.44 Register 44 (0x2C)

Figure 262. Register 44 (0x2C)

7	6	5	4	3	2	1	0
Reserved							LBPD
R/W							R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 202. Register 44 (0x2C) Field Descriptions

Bit	Field	Type	Reset	Description
7-1	Reserved	R/W	0	Reserved
0	LBPD	R/W	0	LDO bandgap power up/down control. LDO bandgap power/up down control on Test mode. 0: Power down 1: Power up

13.3.45 Register 63 (0x3F)

Figure 263. Register 63 (0x3F)

7	6	5	4	3	2	1	0
PWD1
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 203. Register 63 (0x3F) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PWD1	R/W	0	Password1 First word of password. Both words of password must be correctly set in order to unlock test registers. When locked, writing to test registers are inhibited and reading them will return 0.

13.3.46 Register 64 (0x40)

Figure 264. Register 64 (0x40)

7	6	5	4	3	2	1	0
PWD2
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 204. Register 64 (0x40) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PWD2	R/W	0	Password2 First word of password. Both words of password must be correctly set in order to unlock test registers. When locked, writing to test registers are inhibited and reading them will return 0.

13.3.47 Register 65 (0x41)

Figure 265. Register 65 (0x41)

7	6	5	4	3	1	0
Reserved				TSEL
R/W				R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 205. Register 65 (0x41) Field Descriptions

Bit	Field	Type	Reset	Description
7-4	Reserved	R/W	0	Reserved
3-0	TSEL	R/W	0	Test Mode Selection (No longer need) 0: Normal 1:SCAN 2:IDDQ 3:VOH 4:VOL 5: VIL 6:VIH 7:HI-Z

13.3.48 Register 70 (0x46)

Figure 266. Register 70 (0x46)

7	6	5	4	3	1	0
Left Channel DIFF Manual Offset (Q5.2)
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 206. Register 70 (0x46) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Left Channel DIFF Manual Offset (Q5.2)	R/W	0	Add manual offset to the left channel DIFF offset compensator. Observed offset delta: 0111111 : -15.75 mV 0111110 : -15.50 mV 0111101 : -15.25 mV … 0000001 : -0.25 mV 0000000 : 0.0 mV 1111111 : 0.25 mV … 1000010 : 15.50 mV 1000001 : 15.75 mV 1000000 : 16.0 mV

13.3.49 Register 71 (0x47)

Figure 267. Register 71 (0x47)

7	6	5	4	3	1	0
Left Channel CMFB Manual Offset (Q6.2)
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 207. Register 71 (0x47) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Left Channel CMFB Manual Offset (Q6.2)	R/W	0	Add manual offset to the left channel CMFB offset compensator. Observed offset delta: 0111111 : -31.75 mV 0111110 : -31.50 mV 0111101 : -31.25 mV … 0000001 : -0.25 mV 0000000 : 0.0 mV 1111111 : 0.25 mV … 1000010 : 31.50 mV 1000001 : 31.75 mV 1000000 : 32.0 mV

13.3.50 Register 72 (0x48)

Figure 268. Register 72 (0x48)

7	6	5	4	3	1	0
Right Channel DIFF Manual Offset (Q5.2)
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 208. Register 72 (0x48) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Right Channel DIFF Manual Offset (Q5.2)	R/W	0	Add manual offset to the right channel DIFF offset compensator. Observed offset delta: 0111111 : -15.75 mV 0111110 : -15.50 mV 0111101 : -15.25 mV … 0000001 : -0.25 mV 0000000 : 0.0 mV 1111111 : 0.25 mV … 1000010 : 15.50 mV 1000001 : 15.75 mV 1000000 : 16.0 mV

13.3.51 Register 73 (0x49)

Figure 269. Register 73 (0x49)

7	6	5	4	3	1	0
Right Channel CMFB Manual Offset (Q6.2)
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 209. Register 73 (0x49) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Right Channel CMFB Manual Offset (Q6.2)	R/W	0	Add manual offset to the right channel CMFB offset compensator. Observed offset delta: 0111111 : -31.75 mV 0111110 : -31.50 mV 0111101 : -31.25 mV … 0000001 : -0.25 mV 0000000 : 0.0 mV 1111111 : 0.25 mV … 1000010 : 31.50 mV 1000001 : 31.75 mV 1000000 : 32.0 mV

13.3.52 Register 74 (0x4A)

Figure 270. Register 74 (0x4A)

7	6	5	4	3	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 210. Register 74 (0x4A) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.53 Register 75 (0x4B)

Figure 271. Register 75 (0x4B)

7	6	5	4	3	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 211. Register 75 (0x4B) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.54 Register 76 (0x4C)

Figure 272. Register 76 (0x4C)

7	6	5	4	3	1	0
Reserved						Left Channel DIFF Monitor(8)
R/W						R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 212. Register 76 (0x4C) Field Descriptions

Bit	Field	Type	Reset	Description
7-1	Reserved	R/W	0	Reserved
0	Left Channel DIFF Monitor(8)	R		This register shows the approximation of original / compensated left channel DIFF offset. Observed offset delta: 0111111 : 63.75 mV 0111110 : 63.50 mV 0111101 : 63.25 mV … 0000001 : 0.25 mV 0000000 : 0.0 mV 1111111 : -0.25 mV … 1000010 : -63.50 mV 1000001 : -63.75 mV 1000000 : -64.0 mV

13.3.55 Register 77 (0x4D)

Figure 273. Register 77 (0x4D)

7	6	5	4	3	1	0
Left Channel DIFF Monitor(7:0)
R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 213. Register 77 (0x4D) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Left Channel DIFF Monitor(7:0)	R		This register shows the approximation of original / compensated left channel DIFF offset. Observed offset delta: 0111111 : 63.75 mV 0111110 : 63.50 mV 0111101 : 63.25 mV … 0000001 : 0.25 mV 0000000 : 0.0 mV 1111111 : -0.25 mV … 1000010 : -63.50 mV 1000001 : -63.75 mV 1000000 : -64.0 mV

13.3.56 Register 78 (0x4E)

Figure 274. Register 78 (0x4E)

7	6	5	4	3	1	0
Reserved			I048
R/W			RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 214. Register 78 (0x4E) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W	0	Reserved
4-0	I048	R/W	0	FS Det 48 kHz Min Range . Minimum OSC count in LRCLK for 48 kHz detection. Decimal Value 863.

13.3.57 Register 79 (0x4F)

Figure 275. Register 79 (0x4F)

7	6	5	4	3	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 215. Register 79 (0x4F) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.58 Register 80 (0x50)

Figure 276. Register 80 (0x50)

7	6	5	4	3	1	0
Reserved			X048
R/W			RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 216. Register 80 (0x50) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W	0	Reserved
4-0	X048	R/W	0	FS Det 48 kHz Max Range. Minimum OSC count in LRCLK for 48 kHz detection. Decimal Value 2479.

13.3.59 Register 81 (0x51)

Figure 277. Register 81 (0x51)

7	6	5	4	3	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 217. Register 81 (0x51) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.60 Register 82 (0x52)

Figure 278. Register 82 (0x52)

7	6	5	4	3	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 218. Register 82 (0x52) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.61 Register 83 (0x53)

Figure 279. Register 83 (0x53)

7	6	5	4	3	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 219. Register 83 (0x53) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.62 Register 84 (0x54)

Figure 280. Register 84 (0x54)

7	6	5	4	3	1	0
Reserved						Left Channel CMFB Monitor (8)
R/W						R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 220. Register 84 (0x54) Field Descriptions

Bit	Field	Type	Reset	Description
7-1	Reserved	R/W	0	Reserved
0	Left Channel CMFB Monitor(8)	R		This register shows the approximation of original / compensated left channel CMFB offset. Observed offset delta: 0111111 : 63.75 mV 0111110 : 63.50 mV 0111101 : 63.25 mV … 0000001 : 0.25 mV 0000000 : 0.0 mV 1111111 : -0.25 mV … 1000010 : -63.50 mV 1000001 : -63.75 mV 1000000 : -64.0 mV

13.3.63 Register 85 (0x55)

Figure 281. Register 85 (0x55)

7	6	5	4	3	1	0
Left Channel CMFB Monitor (7:0)
R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 221. Register 85 (0x55) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Left Channel CMFB Monitor (7:0)	R		This register shows the approximation of original / compensated left channel CMFB offset. Observed offset delta: 0111111 : 63.75 mV 0111110 : 63.50 mV 0111101 : 63.25 mV … 0000001 : 0.25 mV 0000000 : 0.0 mV 1111111 : –0.25 mV … 1000010 : –63.50 mV 1000001 : –63.75 mV 1000000 : –64.0 mV

13.3.64 Register 86 (0x56)

Figure 282. Register 86 (0x56)

7	6	5	4	3	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 222. Register 86 (0x56) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.65 Register 87 (0x57)

Figure 283. Register 87 (0x57)

7	6	5	4	3	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 223. Register 87 (0x57) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.66 Register 88 (0x58)

Figure 284. Register 88 (0x58)

7	6	5	4	3	1	0
Reserved						Right Channel DIFF Monitor (8)
R/W						R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 224. Register 88 (0x58) Field Descriptions

Bit	Field	Type	Reset	Description
7-1	Reserved	R/W	0	Reserved
0	Right Channel DIFF Monitor (8)	R		This register shows the approximation of original / compensated right channel DIFF offset. Observed offset delta: 0111111 : 63.75 mV 0111110 : 63.50 mV 0111101 : 63.25 mV … 0000001 : 0.25 mV 0000000 : 0.0 mV 1111111 : -0.25 mV … 1000010 : -63.50 mV 1000001 : -63.75 mV 1000000 : -64.0 mV

13.3.67 Register 89 (0x59)

Figure 285. Register 89 (0x59)

7	6	5	4	3	1	0
Right Channel DIFF Monitor (7:0)
R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 225. Register 89 (0x59) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Right Channel DIFF Monitor (7:0)	R		This register shows the approximation of original / compensated right channel DIFF offset. Observed offset delta: 0111111 : 63.75 mV 0111110 : 63.50 mV 0111101 : 63.25 mV … 0000001 : 0.25 mV 0000000 : 0.0 mV 1111111 : -0.25 mV … 1000010 : -63.50 mV 1000001 : -63.75 mV 1000000 : -64.0 mV

13.3.68 Register 90 (0x5A)

Figure 286. Register 90 (0x5A)

7	6	5	4	3	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 226. Register 90 (0x5A) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.69 Register 91 (0x5B)

Figure 287. Register 91 (0x5B)

7	6	5	4	3	1	0
Reserved
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 227. Register 91 (0x5B) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Reserved	R/W	0	Reserved

13.3.70 Register 92 (0x5C)

Figure 288. Register 92 (0x5C)

7	6	5	4	3	1	0
Reserved						Right Channel CMFB Monitor (8)
R/W						R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 228. Register 92 (0x5C) Field Descriptions

Bit	Field	Type	Reset	Description
7-1	Reserved	R/W	0	Reserved
0	Right Channel CMFB Monitor(8)	R		This register shows the approximation of original / compensated right channel CMFB offset. Observed offset delta: 0111111 : 63.75 mV 0111110 : 63.50 mV 0111101 : 63.25 mV … 0000001 : 0.25 mV 0000000 : 0.0 mV 1111111 : –0.25 mV … 1000010 : –63.50 mV 1000001 : –63.75 mV 1000000 : –64.0 mV

13.3.71 Register 93 (0x5D)

Figure 289. Register 93 (0x5D)

7	6	5	4	3	1	0
Right Channel CMFB Monito r(7:0)
R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 229. Register 93 (0x5D) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	Right Channel CMFB Monitor (7:0)	R		This register shows the approximation of original / compensated right channel CMFB offset. Observed offset delta: 0111111 : 63.75 mV 0111110 : 63.50 mV 0111101 : 63.25 mV … 0000001 : 0.25 mV 0000000 : 0.0 mV 1111111 : –0.25 mV … 1000010 : –63.50 mV 1000001 : –63.75 mV 1000000 : –64.0 mV

13.4 DSP Memory Map

Table 230. Memory Map — Book 0x78 (120)⁽¹⁾

SUB ADDRESS	PAGE	REGISTER NAME	NUMBER OF BYTES / FORMAT	DEFAULT VALUE	DESCRIPTION
LEVEL METER
0x54	0x0C	Level Meter Left Output	4 / 1.31	0x000000--	Level Meter Left Output
0x58	0x0C	Level Meter Right Output	4 / 1.31	0x000000--	Level Meter Right Output
SECONDARY EQ LEFT 12 BQS
0x08	0x15	CH-L BQ 1 B0	4 / 5.27	0x7FFFFFFF	Left BQ coefficient
0x0C	0x15	CH-L BQ 1 B1	4 / 6.26	0x00000000	Left BQ coefficient
0x10	0x15	CH-L BQ 1 B2	4 / 5.27	0x00000000	Left BQ coefficient
0x14	0x15	CH-L BQ 1 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x18	0x15	CH-L BQ 1 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x1C	0x15	CH-L BQ 2 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x20	0x15	CH-L BQ 2 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x24	0x15	CH-L BQ 2 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x28	0x15	CH-L BQ 2 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x2C	0x15	CH-L BQ 2 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x30	0x15	CH-L BQ 3 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x34	0x15	CH-L BQ 3 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x38	0x15	CH-L BQ 3 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x3C	0x15	CH-L BQ 3 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x40	0x15	CH-L BQ 3 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x44	0x15	CH-L BQ 4 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x48	0x15	CH-L BQ 4 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x4C	0x15	CH-L BQ 4 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x50	0x15	CH-L BQ 4 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x54	0x15	CH-L BQ 4 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x58	0x15	CH-L BQ 5 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x5C	0x15	CH-L BQ 5 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x60	0x15	CH-L BQ 5 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x64	0x15	CH-L BQ 5 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x68	0x15	CH-L BQ 5 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x6C	0x15	CH-L BQ 6 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x70	0x15	CH-L BQ 6 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x74	0x15	CH-L BQ 6 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x78	0x15	CH-L BQ 6 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x7C	0x15	CH-L BQ 6 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x08	0x16	CH-L BQ 7 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x0C	0x16	CH-L BQ 7 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x10	0x16	CH-L BQ 7 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x14	0x16	CH-L BQ 7 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x18	0x16	CH-L BQ 7 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x1C	0x16	CH-L BQ 8 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x20	0x16	CH-L BQ 8 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x24	0x16	CH-L BQ 8 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x28	0x16	CH-L BQ 8 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x2C	0x16	CH-L BQ 8 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x30	0x16	CH-L BQ 9 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x34	0x16	CH-L BQ 9 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x38	0x16	CH-L BQ 9 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x3C	0x16	CH-L BQ 9 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x40	0x16	CH-L BQ 9 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x44	0x16	CH-L BQ 10 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x48	0x16	CH-L BQ 10 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x4C	0x16	CH-L BQ 10 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x50	0x16	CH-L BQ 10 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x54	0x16	CH-L BQ 10 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x58	0x16	CH-L BQ 11 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x5C	0x16	CH-L BQ 11 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x60	0x16	CH-L BQ 11 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x64	0x16	CH-L BQ 11 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x68	0x16	CH-L BQ 11 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x6C	0x16	CH-L BQ 12 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x70	0x16	CH-L BQ 12 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x74	0x16	CH-L BQ 12 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x78	0x16	CH-L BQ 12 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x7C	0x16	CH-L BQ 12 A2	4 / 1.31	0x00000000	Left BQ coefficient
SECONDARY EQ RIGHT 12 BQS
0x08	0x17	CH-R BQ 1 B0	4 / 5.27	0x7FFFFFFF	Right BQ coefficient
0x0C	0x17	CH-R BQ 1 B1	4 / 6.26	0x00000000	Right BQ coefficient
0x10	0x17	CH-R BQ 1 B2	4 / 5.27	0x00000000	Right BQ coefficient
0x14	0x17	CH-R BQ 1 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x18	0x17	CH-R BQ 1 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x1C	0x17	CH-R BQ 2 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x20	0x17	CH-R BQ 2 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x24	0x17	CH-R BQ 2 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x28	0x17	CH-R BQ 2 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x2C	0x17	CH-R BQ 2 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x30	0x17	CH-R BQ 3 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x34	0x17	CH-R BQ 3 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x38	0x17	CH-R BQ 3 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x3C	0x17	CH-R BQ 3 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x40	0x17	CH-R BQ 3 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x44	0x17	CH-R BQ 4 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x48	0x17	CH-R BQ 4 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x4C	0x17	CH-R BQ 4 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x50	0x17	CH-R BQ 4 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x54	0x17	CH-R BQ 4 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x58	0x17	CH-R BQ 5 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x5C	0x17	CH-R BQ 5 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x60	0x17	CH-R BQ 5 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x64	0x17	CH-R BQ 5 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x68	0x17	CH-R BQ 5 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x6C	0x17	CH-R BQ 6 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x70	0x17	CH-R BQ 6 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x74	0x17	CH-R BQ 6 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x78	0x17	CH-R BQ 6 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x7C	0x17	CH-R BQ 6 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x08	0x18	CH-R BQ 7 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x0C	0x18	CH-R BQ 7 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x10	0x18	CH-R BQ 7 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x14	0x18	CH-R BQ 7 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x18	0x18	CH-R BQ 7 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x1C	0x18	CH-R BQ 8 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x20	0x18	CH-R BQ 8 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x24	0x18	CH-R BQ 8 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x28	0x18	CH-R BQ 8 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x2C	0x18	CH-R BQ 8 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x30	0x18	CH-R BQ 9 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x34	0x18	CH-R BQ 9 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x38	0x18	CH-R BQ 9 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x3C	0x18	CH-R BQ 9 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x40	0x18	CH-R BQ 9 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x44	0x18	CH-R BQ 10 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x48	0x18	CH-R BQ 10 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x4C	0x18	CH-R BQ 10 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x50	0x18	CH-R BQ 10 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x54	0x18	CH-R BQ 10 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x58	0x18	CH-R BQ 11 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x5C	0x18	CH-R BQ 11 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x60	0x18	CH-R BQ 11 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x64	0x18	CH-R BQ 11 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x68	0x18	CH-R BQ 11 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x6C	0x18	CH-R BQ 12 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x70	0x18	CH-R BQ 12 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x74	0x18	CH-R BQ 12 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x78	0x18	CH-R BQ 12 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x7C	0x18	CH-R BQ 12 A2	4 / 1.31	0x00000000	Right BQ coefficient
SECONDARY BQ GAIN SCALE AND VOLUME
0x08	0x19	Left Gain	4 / 8.24		Gain
0x0C	0x19	Right Gain	4 / 8.24		Gain
BANK SWITCH
0x08	0x14	Left Gain	4 / 32.0	0x00000000	Needs swap flag to run -

(1) The registers in this table do not require the swap flag to work

Table 231. Memory Map — Book 0x8C (140)⁽¹⁾

SUB ADDRESS	PAGE	REGISTER NAME	NUMBER OF BYTES / FORMAT	DEFAULT VALUE	DESCRIPTION
DSP MEMORY UPDATE
0x10	0x01	DSP Memory Swap Flag	4 / 32.0	0x00000000	DSP Memory Swap Flag
MAIN EQ LEFT 12 BQS
0x58	0x1B	CH-L BQ 1 B0	4 / 5.27	0x7FFFFFFF	Left BQ coefficient
0x5C	0x1B	CH-L BQ 1 B1	4 / 6.26	0x00000000	Left BQ coefficient
0x60	0x1B	CH-L BQ 1 B2	4 / 5.27	0x00000000	Left BQ coefficient
0x64	0x1B	CH-L BQ 1 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x68	0x1B	CH-L BQ 1 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x6C	0x1B	CH-L BQ 2 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x70	0x1B	CH-L BQ 2 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x74	0x1B	CH-L BQ 2 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x78	0x1B	CH-L BQ 2 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x7C	0x1B	CH-L BQ 2 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x08	0x1C	CH-L BQ 3 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x0C	0x1C	CH-L BQ 3 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x10	0x1C	CH-L BQ 3 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x14	0x1C	CH-L BQ 3 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x18	0x1C	CH-L BQ 3 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x1C	0x1C	CH-L BQ 4 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x20	0x1C	CH-L BQ 4 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x24	0x1C	CH-L BQ 4 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x28	0x1C	CH-L BQ 4 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x2C	0x1C	CH-L BQ 4 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x30	0x1C	CH-L BQ 5 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x34	0x1C	CH-L BQ 5 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x38	0x1C	CH-L BQ 5 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x3C	0x1C	CH-L BQ 5 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x40	0x1C	CH-L BQ 5 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x44	0x1C	CH-L BQ 6 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x48	0x1C	CH-L BQ 6 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x4C	0x1C	CH-L BQ 6 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x50	0x1C	CH-L BQ 6 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x54	0x1C	CH-L BQ 6 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x58	0x1C	CH-L BQ 7 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x5C	0x1C	CH-L BQ 7 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x60	0x1C	CH-L BQ 7 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x64	0x1C	CH-L BQ 7 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x68	0x1C	CH-L BQ 7 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x6C	0x1C	CH-L BQ 8 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x70	0x1C	CH-L BQ 8 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x74	0x1C	CH-L BQ 8 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x78	0x1C	CH-L BQ 8 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x7C	0x1C	CH-L BQ 8 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x08	0x1D	CH-L BQ 9 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x0C	0x1D	CH-L BQ 9 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x10	0x1D	CH-L BQ 9 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x14	0x1D	CH-L BQ 9 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x18	0x1D	CH-L BQ 9 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x1C	0x1D	CH-L BQ 10 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x20	0x1D	CH-L BQ 10 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x24	0x1D	CH-L BQ 10 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x28	0x1D	CH-L BQ 10 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x2C	0x1D	CH-L BQ 10 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x30	0x1D	CH-L BQ 11 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x34	0x1D	CH-L BQ 11 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x38	0x1D	CH-L BQ 11 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x3C	0x1D	CH-L BQ 11 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x40	0x1D	CH-L BQ 11 A2	4 / 1.31	0x00000000	Left BQ coefficient
0x44	0x1D	CH-L BQ 12 B0	4 / 1.31	0x7FFFFFFF	Left BQ coefficient
0x48	0x1D	CH-L BQ 12 B1	4 / 2.30	0x00000000	Left BQ coefficient
0x4C	0x1D	CH-L BQ 12 B2	4 / 1.31	0x00000000	Left BQ coefficient
0x50	0x1D	CH-L BQ 12 A1	4 / 2.30	0x00000000	Left BQ coefficient
0x54	0x1D	CH-L BQ 12 A2	4 / 1.31	0x00000000	Left BQ coefficient
MAIN EQ RIGHT 12 BQS
0x58	0x1D	CH-R BQ 1 B0	4 / 5.27	0x7FFFFFFF	Right BQ coefficient
0x5C	0x1D	CH-R BQ 1 B1	4 / 6.26	0x00000000	Right BQ coefficient
0x60	0x1D	CH-R BQ 1 B2	4 / 5.27	0x00000000	Right BQ coefficient
0x64	0x1D	CH-R BQ 1 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x68	0x1D	CH-R BQ 1 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x6C	0x1D	CH-R BQ 2 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x70	0x1D	CH-R BQ 2 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x74	0x1D	CH-R BQ 2 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x78	0x1D	CH-R BQ 2 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x7C	0x1D	CH-R BQ 2 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x08	0x1E	CH-R BQ 3 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x8C	0x1E	CH-R BQ 3 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x10	0x1E	CH-R BQ 3 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x14	0x1E	CH-R BQ 3 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x18	0x1E	CH-R BQ 3 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x1C	0x1E	CH-R BQ 4 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x20	0x1E	CH-R BQ 4 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x24	0x1E	CH-R BQ 4 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x28	0x1E	CH-R BQ 4 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x2C	0x1E	CH-R BQ 4 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x30	0x1E	CH-R BQ 5 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x34	0x1E	CH-R BQ 5 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x38	0x1E	CH-R BQ 5 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x3C	0x1E	CH-R BQ 5 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x40	0x1E	CH-R BQ 5 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x44	0x1E	CH-R BQ 6 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x48	0x1E	CH-R BQ 6 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x4C	0x1E	CH-R BQ 6 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x50	0x1E	CH-R BQ 6 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x54	0x1E	CH-R BQ 6 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x58	0x1E	CH-R BQ 7 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x5C	0x1E	CH-R BQ 7 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x60	0x1E	CH-R BQ 7 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x64	0x1E	CH-R BQ 7 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x68	0x1E	CH-R BQ 7 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x6C	0x1E	CH-R BQ 8 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x70	0x1E	CH-R BQ 8 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x74	0x1E	CH-R BQ 8 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x78	0x1E	CH-R BQ 8 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x7C	0x1E	CH-R BQ 8 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x08	0x1F	CH-R BQ 9 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x0C	0x1F	CH-R BQ 9 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x10	0x1F	CH-R BQ 9 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x14	0x1F	CH-R BQ 9 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x18	0x1F	CH-R BQ 9 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x1C	0x1F	CH-R BQ 10 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x20	0x1F	CH-R BQ 10 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x24	0x1F	CH-R BQ 10 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x28	0x1F	CH-R BQ 10 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x2C	0x1F	CH-R BQ 10 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x30	0x1F	CH-R BQ 11 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x34	0x1F	CH-R BQ 11 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x38	0x1F	CH-R BQ 11 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x3C	0x1F	CH-R BQ 11 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x40	0x1F	CH-R BQ 11 A2	4 / 1.31	0x00000000	Right BQ coefficient
0x44	0x1F	CH-R BQ 12 B0	4 / 1.31	0x7FFFFFFF	Right BQ coefficient
0x48	0x1F	CH-R BQ 12 B1	4 / 2.30	0x00000000	Right BQ coefficient
0x4C	0x1F	CH-R BQ 12 B2	4 / 1.31	0x00000000	Right BQ coefficient
0x50	0x1F	CH-R BQ 12 A1	4 / 2.30	0x00000000	Right BQ coefficient
0x54	0x1F	CH-R BQ 12 A2	4 / 1.31	0x00000000	Right BQ coefficient
MAIN BQ GAIN SCALE AND VOLUME
0x58	0x1F	Left Gain	4 / 8.24	0x01000000	Gain
0x5C	0x1F	Right Gain	4 / 8.24	0x01000000	Gain
DPEQ SENSE BQ
0x6C	0x1F	BQ B0	4 / 1.31	0x7FFFFFFF	DPEQ sense BQ coefficient
0x70	0x1F	BQ B1	4 / 1.31	0x00000000	DPEQ sense BQ coefficient
0x74	0x1F	BQ B2	4 / 1.31	0x00000000	DPEQ sense BQ coefficient
0x78	0x1F	BQ A1	4 / 1.31	0x00000000	DPEQ sense BQ coefficient
0x7C	0x1F	BQ A2	4 / 1.31	0x00000000	DPEQ sense BQ coefficient
DPEQ HIGH LEVEL PATH BQ
0x08	0x20	BQ B0	4 / 1.31	0x7FFFFFFF	DPEQ high BQ coefficient
0x0C	0x20	BQ B1	4 / 1.31	0x00000000	DPEQ high BQ coefficient
0x10	0x20	BQ B2	4 / 1.31	0x00000000	DPEQ high BQ coefficient
0x14	0x20	BQ A1	4 / 1.31	0x00000000	DPEQ high BQ coefficient
0x18	0x20	BQ A2	4 / 1.31	0x00000000	DPEQ high BQ coefficient
DPEQ LOW LEVEL PATH BQ
0x1C	0x20	BQ B0	4 / 1.31	0x7FFFFFFF	DPEQ low BQ coefficient
0x20	0x20	BQ B1	4 / 1.31	0x00000000	DPEQ low BQ coefficient
0x24	0x20	BQ B2	4 / 1.31	0x00000000	DPEQ low BQ coefficient
0x28	0x20	BQ A1	4 / 1.31	0x00000000	DPEQ low BQ coefficient
0x2C	0x20	BQ A2	4 / 1.31	0x00000000	DPEQ low BQ coefficient
DRC 1 BQ
0x30	0x20	BQ B0	4 / 1.31	0x9D8E8900	DRC 1 BQ coefficient
0x34	0x20	BQ B1	4 / 1.31	0x007BFC00	DRC 1 BQ coefficient
0x38	0x20	BQ B2	4 / 1.31	0x007BFC00	DRC 1 BQ coefficient
0x3C	0x20	BQ A1	4 / 1.31	0x7040C300	DRC 1 BQ coefficient
0x40	0x20	BQ A2	4 / 1.31	0x9D8E8900	DRC 1 BQ coefficient
DRC 2 BQ
0x44	0x20	BQ B0	4 / 1.31	0x70BCBF00	DRC 2 BQ coefficient
0x48	0x20	BQ B1	4 / 1.31	0x007BFC00	DRC 2 BQ coefficient
0x4C	0x20	BQ B2	4 / 1.31	0x007BFC00	DRC 2 BQ coefficient
0x50	0x20	BQ A1	4 / 1.31	0x7040C300	DRC 2 BQ coefficient
0x54	0x20	BQ A2	4 / 1.31	0x9D8E8900	DRC 2 BQ coefficient
DPEQ CONTROL
0x58	0x20	Alpha	4 / 1.31	0x02DEAD00	DPEQ Sense Energy Time constant
0x5C	0x20	Gain	4 / 1.31	0x74013901	DPEQ Threshold Gain
0x60	0x20	Offset	4 / 1.31	0x0020C49B	DPEQ Threshold Offset
LEVER METER
0x64	0x20	Level Meter Alpha	4 / 1.31	0x00A7264A	Level meter Energy Time constant
DRC SUM
0x68	0x20	DRC 1 sum	4 / 1.31	0x7FFFFFFF	DRC1 Mixer Gain
0x6C	0x20	DRC 2 sum	4 / 1.31	0x00000000	DRC2 Mixer Gain
DRC 1
0x70	0x20	DRC1 Energy	4 / 1.31	0x7FFFFFFF	DRC1 Energy Time constant
0x74	0x20	DRC1 Attack	4 / 1.31	0x7FFFFFFF	DRC1 Attack Time constant
0x78	0x20	DRC1 Decay	4 / 1.31	0x7FFFFFFF	DRC1 Decay Time constant
0x7C	0x20	K0_1	4 / 9.23	0x00000000	DRC1 Region 1 Slope (comp/Exp)
0x08	0x21	K1_1	4 / 9.23	0x00000000	DRC1 Region 2 Slope (comp/Exp)
0x0C	0x21	K2_1	4 / 9.23	0x00000000	DRC1 Region 3 Slope (comp/Exp)
0x10	0x21	T1_1	4 / 9.23	0xE7000000	DRC1 Threshold 1
0x14	0x21	T2_1	4 / 9.23	0xFE800000	DRC1 Threshold 2
0x18	0x21	Offset 1	4 / 9.23	0x00000000	DRC1 Offset 1
0x1C	0x21	Offset 2	4 / 9.23	0x00000000	DRC1 Offset 2
DRC 2
0x20	0x21	DRC2 Energy	4 / 1.31	0x7FFFFFFF	DRC2 Energy Time constant
0x24	0x21	DRC2 Attack	4 / 1.31	0x7FFFFFFF	DRC2 Attack Time constant
0x28	0x21	DRC2 Decay	4 / 1.31	0x7FFFFFFF	DRC2 Decay Time constant
0x2C	0x21	K0_1	4 / 9.23	0x00000000	DRC2 Region 1 Slope (comp/Exp)
0x30	0x21	K1_1	4 / 9.23	0x00000000	DRC2 Region 2 Slope (comp/Exp)
0x34	0x21	K2_1	4 / 9.23	0x00000000	DRC2 Region 3 Slope (comp/Exp)
0x38	0x21	T1_1	4 / 9.23	0xE7000000	DRC2 Threshold 1
0x3C	0x21	T2_1	4 / 9.23	0xFE800000	DRC2 Threshold 2
0x40	0x21	Offset 1	4 / 9.23	0x00000000	DRC2 Offset 1
0x44	0x21	Offset 2	4 / 9.23	0x00000000	DRC2 Offset 2
FINE VOLUME OUTPUT
0x48	0x21	Fine volume left	4 / 2.30	0x3FFFFFFF	Left Channel Fine Volume Gain
0x4C	0x21	Fine volume right	4 / 2.30	0x3FFFFFFF	Right Channel Fine Volume Gain
INPUT MIXER
0x50	0x21	Left in to left out	4 / 9.23	0x00800000	Left Channel Mixer Left Input Gain
0x54	0x21	Right in to left out	4 / 9.23	0x00000000	Left Channel Mixer Right Input Gain
0x58	0x21	Left in to right out	4 / 9.23	0x00000000	Right Channel Mixer Left Input Gain
0x5C	0x21	Right in to right out	4 / 9.23	0x00800000	Right Channel Mixer Right Input Gain
DPEQ GAIN SCALE
0x60	0x21	DPEQ sense scale	4 / 6.26	0x40000000	DPEQ Sense Input Gain Scale
BYPASS EQ MUX
0x64	0x21		4 / 32.0	0x00000000
GANG LEFT / RIGHT EQ
0x68	0x21		4 / 32.0	0x00000000
BYPASS WORKLOAD TO SDOUT
0x6C	0x21		4 /32.0	0x00000000
BYPASS TO LEVEL METER BIT
0x70	0x21		4 / 32.0	0x00000000
THD BOOST
0x74	0x21		4 / 9.23	0x00400000
AGL
0x78	0x21	Attack Threshold	4 / 5.27	0x40000000	Threshold linear
0x7C	0x21	Softening Filter Alpha	4 / 1.31	0x06153BD1	AGL Alpha Time constant
0x08	0x22	Attack Rate	4 / 1.31	0x0001B4E8	AGL Attack Time constant
0x0C	0x22	AGL Enable	4 / 1.31	0x40000000	AGL Enable Mux
0x10	0x22	Chomp	4 / 1.31	0x0020C49C
0x14	0x22	Softening Filter Omega	4 / 1.31	0x79EAC42F	AGL Omega Time constant
0x18	0x22	Release Rate	4 / 1.31	0x00002BB1	AGL Release Time constant
0x1C	0x22	Volume	4 / 1.31	0x7FFFFFFF	AGL Volume

(1) Will be set to default anytime a DSP reset, CP error or device standby occurs. Clock errors and frequency changes cause DSP reset. The clocks should be stable when using these mux in non-default state. Always poll muxes status and set muxes prior to use in application. TI recommends that these muxes are repeatedly polled and refreshed during application in the event a DSP reset occurred that cleared the muxes.

封装选项

机械数据 (封装 | 引脚)

散热焊盘机械数据 (封装 | 引脚)

订购信息

13 Register Maps

13.1 Registers - Page 0

13.1.1 Register 1 (0x01)

Table 34. Register 1 (0x01) Field Descriptions

13.1.2 Register 2 (0x02)

Table 35. Register 2 (0x02) Field Descriptions

13.1.3 Register 3 (0x03)

Table 36. Register 3 (0x03) Field Descriptions

13.1.4 Register 4 (0x04)

Table 37. Register 4 (0x04) Field Descriptions

13.1.5 Register 5 (0x05)

Table 38. Register 5 (0x05) Field Descriptions

13.1.6 Register 6 (0x06)

Table 39. Register 6 (0x06) Field Descriptions

13.1.7 Register 7 (0x07)

Table 40. Register 7 (0x07) Field Descriptions

13.1.8 Register 8 (0x08)

Table 41. Register 8 (0x08) Field Descriptions

13.1.9 Register 9 (0x09)

Table 42. Register 9 (0x09) Field Descriptions

13.1.10 Register 10 (0x0A)

Table 43. Register 10 (0x0A) Field Descriptions

13.1.11 Register 12 (0x0C)

Table 44. Register 12 (0x0C) Field Descriptions

13.1.12 Register 13 (0x0D)

Table 45. Register 13 (0x0D) Field Descriptions

13.1.13 Register 14 (0x0E)

Table 46. Register 14 (0x0E) Field Descriptions

13.1.14 Register 15 (0x0F)

Table 47. Register 15 (0x0F) Field Descriptions

13.1.15 Register 16 (0x10)

Table 48. Register 16 (0x10) Field Descriptions

13.1.16 Register 17 (0x11)

Table 49. Register 17 (0x11) Field Descriptions

13.1.17 Register 18 (0x12)

Table 50. Register 18 (0x12) Field Descriptions

13.1.18 Register 19 (0x13)

Table 51. Register 19 (0x13) Field Descriptions

13.1.19 Register 20 (0x14)

Table 52. Register 20 (0x14) Field Descriptions

13.1.20 Register 21 (0x15)

Table 53. Register 21 (0x15) Field Descriptions

13.1.21 Register 22 (0x16)

Table 54. Register 22 (0x16) Field Descriptions

13.1.22 Register 23 (0x17)

Table 55. Register 23 (0x17) Field Descriptions

13.1.23 Register 24 (0x18)

Table 56. Register 24 (0x18) Field Descriptions

13.1.24 Register 25 (0x19)

Table 57. Register 25 (0x19) Field Descriptions

13.1.25 Register 26 (0x1A)

Table 58. Register 26 (0x1A) Field Descriptions

13.1.26 Register 27 (0x1B)

Table 59. Register 27 (0x1B) Field Descriptions

13.1.27 Register 28 (0x1C)

Table 60. Register 28 (0x1C) Field Descriptions

13.1.28 Register 29 (0x1D)

Table 61. Register 29 (0x1D) Field Descriptions

13.1.29 Register 30 (0x1E)

Table 62. Register 30 (0x1E) Field Descriptions

13.1.30 Register 31 (0x1F)

Table 63. Register 31 (0x1F) Field Descriptions

13.1.31 Register 32 (0x20)

Table 64. Register 32 (0x20) Field Descriptions

13.1.32 Register 33 (0x21)

Table 65. Register 33 (0x21) Field Descriptions

13.1.33 Register 34 (0x22)

Table 66. Register 34 (0x22) Field Descriptions

13.1.34 Register 35 (0x23)

Table 67. Register 35 (0x23) Field Descriptions

13.1.35 Register 37 (0x25)

Table 68. Register 37 (0x25) Field Descriptions

13.1.36 Register 38 (0x26)

Table 69. Register 38 (0x26) Field Descriptions

13.1.37 Register 39 (0x27)

Table 70. Register 39 (0x27) Field Descriptions