9.3.3.1 Clock Master Mode from Audio Rate Master Clock

In Master Mode, the device generates bit clock and left-right and frame sync clock and outputs them on the appropriate pins. To configure the device in master mode, first put the device into reset, then use registers SCLKO and LRKO (P0-R9). Then reset the LRCK/FS and SCLK divider counters using bits RSCLK and RLRK (P0-R12). Finally, exit reset.

Figure 58 shows a simplified serial port clock tree for the device in master mode.

Figure 58. Simplified Clock Tree for MCLK Sourced Master Mode

In master mode, MCLK is an input and SCLK and LRCK/FS are outputs. SCLK and LRCK/FS are integer divisions of MCLK. Master mode with a non-audio rate master clock source requires external GPIO’s to use the PLL in standalone mode. The PLL should be configured to ensure that the on-chip processor can be driven at the maximum clock rate. The master mode of operation is described in the Clock Master from a Non-Audio Rate Master Clock section.

When used with audio rate master clocks, the register changes that should be done include switching the device into master mode, and setting the divider ratio. An example of the master mode of operations is using 24.576 MHz MCLK as a master clock source and driving the SCLK and LRCK/FS with integer dividers to create 48 kHz sample rate clock output. In master mode, the DAC section of the device is also running from the PLL output. The TAS5780M device is able to meet the specified audio performance while using the internal PLL. However, using the MCLK CMOS oscillator source will have less jitter than the PLL.

To switch the DAC clocks (SDAC in the Figure 57) the following registers should be modified

• Clock Tree Flex Mode (P253-R63 and P253-R64)
• DAC and OSR Source Clock Register (P0-R14). Set to 0x30 (MCLK input, and OSR is set to whatever the DAC source is)
• The DAC clock divider should be 16 f_S.
  • 16 × 48 kHz = 768 kHz
  • 24.576 MHz (MCLK in) / 768 kHz = 32
  • Therefore, the divide ratio for register DDAC (P0-R28) should be set to 32. The register mapping gives 0x00 = 1, therefore 32 must be converter to 0x1F (31dec).

9.3.3.2 Clock Master from a Non-Audio Rate Master Clock

The classic example here is running a 96-kHz sampling system. Given the clock tree for the device (shown in Figure 57), a non-audio clock rate cannot be brought into the MCLK to the PLL in master mode. Therefore, the PLL source must be configured to be a GPIO pin, and the output brought back into another GPIO pin.

Figure 59. Generating Audio Clocks Using Non-Audio Clock Sources

The clock flow through the system is shown in Figure 59. The newly generated MCLK must be brought out of the device on a GPIO pin, then brought into the MCLK pin for integer division to create SCLK and LRCK/FS outputs.

9.3.3.3 Clock Slave Mode with 4-Wire Operation (SCLK, MCLK, LRCK/FS, SDIN)

The TAS5780M device requires a system clock to operate the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the MCLK input and supports up to 50 MHz. The TAS5780M device system-clock detection circuit automatically senses the system-clock frequency. Common audio sampling frequencies in the bands of 32 kHz, (44.1 – 48 kHz), (88.2 – 96 kHz) are supported.

In the presence of a valid bit MCLK, SCLK and LRCK/FS, the device automatically configures the clock tree and PLL to drive the µCDSP as required.

The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the Negative Charge Pump (NCP) automatically. Table 2 shows examples of system clock frequencies for common audio sampling rates.

MCLK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are supported by configuring various PLL and clock-divider registers directly. In slave mode, auto clock mode should be disabled using P0-R37. Additionally, the user can be required to ignore clock error detection if external clocks are not available for some time during configuration or if the clocks presented on the pins of the device are invalid. The extended programmability allows the device to operate in an advanced mode in which the device becomes a clock master and drive the host serial port with LRCK/FS and SCLK, from a non-audio related clock (for example, using a setting of 12 MHz to generate 44.1 kHz [LRCK/FS] and 2.8224 MHz [SCLK]).

Table 2 shows the timing requirements for the system clock input. For optimal performance, use a clock source with low phase jitter and noise. For MCLK timing requirements, refer to the Serial Audio Port Timing – Master Mode section.

9.3.3.4 Clock Slave Mode with SCLK PLL to Generate Internal Clocks (3-Wire PCM)

9.3.3.4.2 PLL Calculation

The TAS5780M device has an on-chip PLL with fractional multiplication to generate the clock frequency required by the Digital Signal Processing blocks. The programmability of the PLL allows operation from a wide variety of clocks that may be available in the system. The PLL input (PLLCKIN) supports clock frequencies from 1 MHz to 50 MHz and is register programmable to enable generation of required sampling rates with fine precision.

The PLL is enabled by default. The PLL can be enabled by writing to P0-R4, D[0]. When the PLL is enabled, the PLL output clock PLLCK is given by Equation 1:

Equation 1.

where

• R = 1, 2, 3,4, ... , 15, 16
• J = 4,5,6, . . . 63, and D = 0000, 0001, 0002, . . . 9999
• K = [J value].[D value]
• P = 1, 2, 3, ... 15

R, J, D, and P are programmable. J is the integer portion of K (the numbers to the left of the decimal point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).

9.3.3.4.2.1 Examples:

• If K = 8.5, then J = 8, D = 5000
• If K = 7.12, then J = 7, D = 1200
• If K = 14.03, then J = 14, D = 0300
• If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied:

• 1 MHz ≤ ( PLLCKIN / P ) ≤ 20 MHz
• 64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz
• 1 ≤ J ≤ 63

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied:

• 6.667 MHz ≤ PLLCLKIN / P ≤ 20 MHz
• 64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz
• 4 ≤ J ≤ 11
• R = 1

When the PLL is enabled,

• f_S = (PLLCLKIN × K × R) / (2048 × P)
• The value of N is selected so that f_S × N = PLLCLKIN x K x R / P is in the allowable range.

Example: MCLK = 12 MHz and f_S = 44.1 kHz, (N=2048)

Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example: MCLK = 12 MHz and f_S = 48.0 kHz, (N=2048)

Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

Values are written to the registers in Table 4.

Table 4. PLL Registers

DIVIDER	FUNCTION	BITS
PLLE	PLL enable	P0-R4, D[0]
PPDV	PLL P	P0-R20, D[3:0]
PJDV	PLL J	P0-R21, D[5:0]
PDDV	PLL D	P0-R22, D[5:0]
		P0-R23, D[7:0]
PRDV	PLL R	P0-R24, D[3:0]

Table 5. PLL Configuration Recommendations

EQUATIONS	DESCRIPTION
fS (kHz)	Sampling frequency
RMCLK	Ratio between sampling frequency and MCLK frequency (MCLK frequency = RMCLK x sampling frequency)
MCLK (MHz)	System master clock frequency at MCLK input (pin 20)
PLL VCO (MHz)	PLL VCO frequency as PLLCK in Figure 57
P	One of the PLL coefficients in Equation 1
PLL REF (MHz)	Internal reference clock frequency which is produced by MCLK / P
M = K × R	The final PLL multiplication factor computed from K and R as described in Equation 1
K = J.D	One of the PLL coefficients in Equation 1
R	One of the PLL coefficients in Equation 1
PLL fS	Ratio between fS and PLL VCO frequency (PLL VCO / fS)
DSP fS	Ratio between operating clock rate and fS (PLL fS / NMAC)
NMAC	The clock divider value in Table 3
DSP CLK (MHz)	The operating frequency as DSPCK in Figure 57
MOD fS	Ratio between DAC operating clock frequency and fS (PLL fS / NDAC)
MOD f (kHz)	DAC operating frequency as DACCK in
NDAC	DAC clock divider value in Table 3
DOSR	OSR clock divider value in Table 3 for generating OSRCK in Figure 57. DOSR must be chosen so that MOD fS / DOSR = 16 for correct operation.
NCP	NCP (negative charge pump) clock divider value in Table 3
CP f	Negative charge pump clock frequency (fS × MOD fS / NCP)
% Error	Percentage of error between PLL VCO / PLL fS and fS (mismatch error). This value is typically zero but can be non-zero especially when K is not an integer (D is not zero). This value can be non-zero only when the TAS5780M device acts as a master.

The previous equations explain how to calculate all necessary coefficients and controls to configure the PLL. Table 6 provides for easy reference to the recommended clock divider settings for the PLL as a Master Clock.

Table 6. Recommended Clock Divider Settings for PLL as Master Clock

fS (kHz)	RMCLK	MCLK (MHz)	PLL VCO (MHz)	P	PLL REF (MHz)	M = K×R	K = J×D	R	PLL fS	DSP fS	NMAC	DSP CLK (MHz)	MOD fS	MOD f (kHz)	NDAC	DOSR	% ERROR	NCP	CP f (kHz)
8	128	1.024	98.304	1	1.024	96	48	2	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	192	1.536	98.304	1	1.536	64	32	2	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	256	2.048	98.304	1	2.048	48	48	1	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	384	3.072	98.304	3	1.024	96	48	2	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	512	4.096	98.304	3	1.365	72	36	2	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	768	6.144	98.304	3	2.048	48	48	1	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	1024	8.192	98.304	3	2.731	36	36	1	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	1152	9.216	98.304	9	1.024	96	48	2	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	1536	12.288	98.304	9	1.365	72	36	2	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	2048	16.384	98.304	9	1.82	54	54	1	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	3072	24.576	98.304	9	2.731	36	36	1	12288	1024	12	8.192	768	6144	16	48	0	4	1536
11.025	128	1.4112	90.3168	1	1.411	64	32	2	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	192	2.1168	90.3168	3	0.706	128	32	4	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	256	2.8224	90.3168	1	2.822	32	32	1	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	384	4.2336	90.3168	3	1.411	64	32	2	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	512	5.6448	90.3168	3	1.882	48	48	1	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	768	8.4672	90.3168	3	2.822	32	32	1	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	1024	11.2896	90.3168	3	3.763	24	24	1	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	1152	12.7008	90.3168	9	1.411	64	32	2	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	1536	16.9344	90.3168	9	1.882	48	48	1	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	2048	22.5792	90.3168	9	2.509	36	36	1	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	3072	33.8688	90.3168	9	3.763	24	24	1	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
16	64	1.024	98.304	1	1.024	96	48	2	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	128	2.048	98.304	1	2.048	48	48	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	192	3.072	98.304	1	3.072	32	32	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	256	4.096	98.304	1	4.096	24	24	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	384	6.144	98.304	3	2.048	48	48	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	512	8.192	98.304	3	2.731	36	36	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	768	12.288	98.304	3	4.096	24	24	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	1024	16.384	98.304	3	5.461	18	18	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	1152	18.432	98.304	3	6.144	16	16	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	1536	24.576	98.304	9	2.731	36	36	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	2048	32.768	98.304	9	3.641	27	27	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	3072	49.152	98.304	9	5.461	18	18	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
22.05	64	1.4112	90.3168	1	1.411	64	32	2	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	128	2.8224	90.3168	1	2.822	32	32	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	192	4.2336	90.3168	3	1.411	64	32	2	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	256	5.6448	90.3168	1	5.645	16	16	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	384	8.4672	90.3168	3	2.822	32	32	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	512	11.2896	90.3168	3	3.763	24	24	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	768	16.9344	90.3168	3	5.645	16	16	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	1024	22.5792	90.3168	3	7.526	12	12	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	1152	25.4016	90.3168	9	2.822	32	32	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	1536	33.8688	90.3168	9	3.763	24	24	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	2048	45.1584	90.3168	9	5.018	18	18	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
32	32	1.024	98.304	1	1.024	96	48	2	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	48	1.536	98.304	1	1.536	64	16	4	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	64	2.048	98.304	1	2.048	48	24	2	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	128	4.096	98.304	1	4.096	24	24	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	192	6.144	98.304	3	2.048	48	48	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	256	8.192	98.304	2	4.096	24	24	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	384	12.288	98.304	3	4.096	24	24	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	512	16.384	98.304	3	5.461	18	18	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	768	24.576	98.304	3	8.192	12	12	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	1024	32.768	98.304	3	10.923	9	9	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	1152	36.864	98.304	9	4.096	24	24	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	1536	49.152	98.304	6	8.192	12	12	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
44.1	32	1.4112	90.3168	1	1.411	64	32	2	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
	64	2.8224	90.3168	1	2.822	32	16	2	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
	128	5.6448	90.3168	1	5.645	16	16	1	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
	192	8.4672	90.3168	3	2.822	32	32	1	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
	256	11.2896	90.3168	2	5.645	16	16	1	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
	384	16.9344	90.3168	3	5.645	16	16	1	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
	512	22.5792	90.3168	3	7.526	12	12	1	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
	768	33.8688	90.3168	3	11.29	8	8	1	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
	1024	45.1584	90.3168	3	15.053	6	6	1	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
48	32	1.536	98.304	1	1.536	64	32	2	2048	1024	2	49.152	128	6144	16	8	0	4	1536
	64	3.072	98.304	1	3.072	32	16	2	2048	1024	2	49.152	128	6144	16	8	0	4	1536
	128	6.144	98.304	1	6.144	16	16	1	2048	1024	2	49.152	128	6144	16	8	0	4	1536
	192	9.216	98.304	3	3.072	32	32	1	2048	1024	2	49.152	128	6144	16	8	0	4	1536
	256	12.288	98.304	2	6.144	16	16	1	2048	1024	2	49.152	128	6144	16	8	0	4	1536
	384	18.432	98.304	3	6.144	16	16	1	2048	1024	2	49.152	128	6144	16	8	0	4	1536
	512	24.576	98.304	3	8.192	12	12	1	2048	1024	2	49.152	128	6144	16	8	0	4	1536
	768	36.864	98.304	3	12.288	8	8	1	2048	1024	2	49.152	128	6144	16	8	0	4	1536
	1024	49.152	98.304	3	16.384	6	6	1	2048	1024	2	49.152	128	6144	16	8	0	4	1536
96	32	3.072	98.304	1	3.072	32	16	2	1024	512	2	49.152	64	6144	16	4	0	4	1536
	48	4.608	98.304	3	1.536	64	32	2	1024	512	2	49.152	64	6144	16	4	0	4	1536
	64	6.144	98.304	1	6.144	16	8	2	1024	512	2	49.152	64	6144	16	4	0	4	1536
	128	12.288	98.304	2	6.144	16	16	1	1024	512	2	49.152	64	6144	16	4	0	4	1536
	192	18.432	98.304	3	6.144	16	16	1	1024	512	2	49.152	64	6144	16	4	0	4	1536
	256	24.576	98.304	4	6.144	16	16	1	1024	512	2	49.152	64	6144	16	4	0	4	1536
	384	36.864	98.304	6	6.144	16	16	1	1024	512	2	49.152	64	6144	16	4	0	4	1536
	512	49.152	98.304	8	6.144	16	16	1	1024	512	2	49.152	64	6144	16	4	0	4	1536

9.3.3.5 Serial Audio Port – Data Formats and Bit Depths

The serial audio interface port is a 3-wire serial port with the signals LRCK/FS (pin 25), SCLK (pin 23), and SDIN (pin 24). SCLK is the serial audio bit clock, used to clock the serial data present on SDIN into the serial shift register of the audio interface. Serial data is clocked into the TAS5780M device on the rising edge of SCLK. The LRCK/FS pin is the serial audio left/right word clock or frame sync when the device is operated in TDM Mode.

The TAS5780M device requires the synchronization of LRCK/FS and system clock, but does not require a specific phase relation between LRCK/FS and system clock.

If the relationship between LRCK/FS and system clock changes more than ±5 MCLK, internal operation is initialized within one sample period and analog outputs are forced to the bipolar zero level until re-synchronization between LRCK/FS and system clock is completed.

If the relationship between LRCK/FS and SCLK are invalid more than 4 LRCK/FS periods, internal operation is initialized within one sample period and analog outputs are forced to the bipolar zero level until re-synchronization between LRCK/FS and SCLK is completed.

9.3.3.5.1 Data Formats and Master/Slave Modes of Operation

The TAS5780M device supports industry-standard audio data formats, including standard I²S and left-justified. Data formats are selected via Register (P0-R40). All formats require binary two's complement, MSB-first audio data; up to 32-bit audio data is accepted. The data formats are detailed in Figure 60 through Figure 65.

The TAS5780M device also supports right-justified, and TDM data. I²S, LJ, RJ, and TDM are selected using Register (P0-R40). All formats require binary 2s complement, MSB-first audio data. Up to 32 bits are accepted. Default setting is I²S and 24 bit word length. The I²S slave timing is shown in Figure 20.

shows a detailed timing diagram for the serial audio interface.

In addition to acting as a I²S slave, the TAS5780M device can act as an I²S master, by generating SCLK and LRCK/FS as outputs from the MCLK input. Table 8 lists the registers used to place the device into Master or Slave mode. Please refer to the Serial Audio Port Timing – Master Mode section for serial audio Interface timing requirements in Master Mode. For Slave Mode timing, please refer to the Serial Audio Port Timing – Slave Mode section.

Table 8. I²S Master Mode Registers

REGISTER	FUNCTION
P0-R9-B0, B4, and B5	I2S Master mode select
P0-R32-D[6:0]	SCLK divider and LRCK/FS divider
P0-R33-D[7:0]

Figure 60. Left Justified Audio Data Format

I²S Data Format; L-channel = LOW, R-channel = HIGH

Figure 61. I²S Audio Data Format

The following data formats are only available in software mode.

Right Justified Data Format; L-channel = HIGH, R-channel = LOW

Figure 62. Right Justified Audio Data Format

TDM Data Format with OFFSET = 0

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

Figure 63. TDM 1 Audio Data Format

TDM Data Format with OFFSET = 1

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

Figure 64. TDM 2 Audio Data Format

TDM Data Format with OFFSET = N

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

Figure 65. TDM 3 Audio Data Format

9.3.3.6 Input Signal Sensing (Power-Save Mode)

The TAS5780M device has a zero-detect function. The zero-detect function can be applied to both channels of data as an AND function or an OR function, via controls provided in the control port in P0-R65-D[2:1].Continuous Zero data cycles are counted by LRCK/FS, and the threshold of decision for analog mute can be set by P0-R59, D[6:4] for the data which is clocked in on the left frame of an I²S signal or Slot 1 of a TDM signal and P0-R59, D[2:0] for the data which is clocked in on the right frame of an I²S signal or Slot 2 of a TDM signal as shown in Table 10. Default values are 0 for both channels.

In Hardware mode, the device uses default values.

9.3.4.1 Example

The following is a sample script for enabling the device:

9.3.5.1 DAC Digital Gain Control

A basic DAC digital gain control with range between 24 dB and –103 dB and mute is available on each channels by P0-R61-D[7:0] for SPK_OUTB± and P0-R62-D[7:0] for SPK_OUTA±. These volume controls all have 0.5 dB step programmability over most gain and attenuation ranges. Table 11 lists the detailed gain versus programmed setting for the basic volume control. Volume can be changed for both SPK_OUTB± and SPK_OUTA± at the same time or independently by P0-R61-D[1:0] . When D[1:0] set 00 (default), independent control is selected. When D[1:0] set 01, SPK_OUTA± accords with SPK_OUTB± volume. When D[1:0] set 10, SPK_OUTA± volume controls the volume for both channels. To set D[1:0] to 11 is prohibited.

Table 11. DAC Digital Gain Control Settings

GAIN SETTING	BINARY DATA	GAIN (dB)	COMMENTS
0	0000-0000	24.0	Positive maximum
1	0000-0001	23.5
. . .	. . .	. . .
46	0010-1110	1.0
47	0010-1111	0.5
48	0011-0000	0.0	No attenuation (default)
49	0011-0001	–0.5
50	0011-0010	–1.0
51	0011-0011	–1.5
. . .	. . .	. . .
253	1111-1101	–102.5
254	1111-1110	–103	Negative maximum
255	1111-1111	–	Negative infinite (Mute)

Ramp-up frequency and ramp-down frequency can be controlled by P0-R63, D[7:6] and D[3:2] as shown in Table 12. Also ramp-up step and ramp-down step can be controlled by P0-R63, D[5:4] and D[1:0] as shown in Table 13.

Table 14. Sample Rates vs Synchronization Signal

Table 15. Amplifier Switching Mode vs. SPK_GAIN/FREQ Voltage

9.3.7.1 Device Overtemperature Protection

The TAS5780M device continuously monitors die temperature to ensure the temperature does not exceed the OTE_THRES level specified in the Recommended Operating Conditions table. If an OTE event occurs, the SPK_FAULT line is pulled low and the SPK_OUTxx outputs transition to high impedance, signifying a fault. This is a non-latched error and the device will attempt to self clear after OTE_CLRTIME has passed.

9.3.7.2 SPK_OUTxx Overcurrent Protection

The TAS5780M device continuously monitors the output current of each amplifier output to ensure the output current does not exceed the OCE_THRES level specified in the Recommended Operating Conditions table. If an OCE event occurs, the SPK_FAULT line is pulled low and the SPK_OUTxx outputs transition to high impedance, signifying a fault. This is a non-latched error and the device will attempt to self clear after OCE_CLRTIME has passed.

9.3.7.3 Internal V_AVDD Undervoltage-Error Protection

The TAS5780M device internally monitors the AVDD net to protect against the AVDD supply dropping unexpectedly. To enable this feature, P1-R5-B0 is used.

9.3.7.4 Internal V_PVDD Undervoltage-Error Protection

If the voltage presented on the PVDD supply drops below the UVE_THRES(PVDD) value listed in the Recommended Operating Conditions table, the SPK_OUTxx outputs transition to high impedance. This is a self-clearing error, which means that once the PVDD level drops below the level listed in the Recommended Operating Conditions table, the device resumes normal operation.

9.3.7.5 Internal V_PVDD Overvoltage-Error Protection

If the voltage presented on the PVDD supply exceeds the OVE_THRES(PVDD) value listed in the Recommended Operating Conditions table, the SPK_OUTxx outputs will transition to high impedance. This is a self-clearing error, which means that once the PVDD level drops below the level listed in the Recommended Operating Conditions table, the device will resume normal operation.

9.3.7.6 External Undervoltage-Error Protection

The SPK_MUTE pin can also be used to monitor a system voltage, such as a LCD TV backlight, a battery pack in portable device, by using a voltage divider created with two resistors (see Figure 66).

• If the SPK_MUTE pin makes a transition from 1 to 0 over 6 ms or more, the device switches into external undervoltage protection mode, which uses two trigger levels.
• When the SPK_MUTE pin level reaches 2 V, soft mute process begins.
• When the SPK_MUTE pin level reaches 1.2 V, analog output mute engages, regardless of digital audio level, and analog output shutdown begins.

Figure 67 shows a timing diagram for external undervoltage error protection.

When the divider is set correctly, any DC voltage can be monitored. Figure 66 shows a 12-V example of how the SPK_MUTE is used for external undervoltage error protection.

Figure 66. SPK_MUTE Used in External Undervoltage Error Protection

Figure 67. SPK_MUTE Timing for External Undervoltage Error Protection

9.3.7.7 Internal Clock Error Notification (CLKE)

When a clock error is detected on the incoming data clock, the TAS5780M device switches to an internal oscillator and continues to the drive the DAC, while attenuating the data from the last known value. Once this process is complete, the DAC outputs will be hard muted to the ground and the class D PWM output will stop switching. The clock error can be monitored at B0-P0-R94 and R95. The clock error status bits are non-latching, except for MCLK halted B0-P0-R95-D[4] and CERF B0-P0-R95-D[0] which are cleared when read.

9.3.9.1 Slave Address

The TAS5780M device has 7 bits for the slave address. The first five bits (MSBs) of the slave address are factory preset to 10011 (0x9x). The next two bits of the address byte are the device select bits which can be user-defined by the ADR1 and ADR0 terminals. A maximum of four devices can be connected on the same bus at one time, which gives a range of 0x90, 0x92, 0x94 and 0x96, as detailed in Table 17. Each TAS5780M device responds when it receives the slave address.

9.3.9.2 Register Address Auto-Increment Mode

Auto-increment mode allows multiple sequential register locations to be written to or read back in a single operation, and is especially useful for block write and read operations. The TAS5780M device supports auto-increment mode automatically. Auto-increment stops at page boundaries.

9.3.9.3 Packet Protocol

A master device must control packet protocol, which consists of start condition, slave address, read/write bit, data if write or acknowledge if read, and stop condition. The TAS5780M device supports only slave receivers and slave transmitters.

Figure 69. Packet Protocol

M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition

9.3.9.4 Write Register

A master can write to any TAS5780M device registers using single or multiple accesses. The master sends a TAS5780M device slave address with a write bit, a register address, and the data. If auto-increment is enabled, the address is that of the starting register, followed by the data to be transferred. When the data is received properly, the index register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. Table 20 shows the write operation.

M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition; W = Write; ACK = Acknowledge

9.3.9.5 Read Register

A master can read the TAS5780M device register. The value of the register address is stored in an indirect index register in advance. The master sends a TAS5780M device slave address with a read bit after storing the register address. Then the TAS5780M device transfers the data which the index register points to. When auto-increment is enabled, the index register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. Table 21 lists the read operation.

M = Master Device; S = Slave Device; St = Start Condition; Sr = Repeated start condition; Sp = Stop Condition; W = Write; R = Read; NACK = Not acknowledge

9.3.9.6 DSP Book, Page, and Register Update

The DSP memory is arranged in books, pages, and registers. Each book has several pages and each page has several registers.

9.4.3.1 Stereo Mode

The familiar stereo mode of operation uses the TAS5780M device to amplify two independent signals, which represent the left and right portions of a stereo signal. These amplified left and right audio signals are presented on differential output pairs shown as SPK_OUTA± and SPK_OUTB±. The routing of the audio data which is presented on the SPK_OUTxx outputs can be changed according to the Audio Process Flow which is used and the configuration of registers P0-R42-D[5:4] and P0-R42-D[1:0]. The familiar stereo mode of operation is shown in .

By default, the TAS5780M device is configured to output the Right frame of a I²S input on the Channel A output and the left frame on the Channel B output.

9.4.3.2 Mono Mode

The mono mode of operation is used to describe operation in which the two outputs of the device are placed in parallel with one another to increase the power sourcing capabilities of the audio output channel. This is also known as Parallel Bridge Tied Load (PBTL).

On the output side of the TAS5780M device, the summation of the devices can be done before the filter in a configuration called Pre-Filter PBTL. However, the two outputs may be required to merge together after the inductor portion of the output filter. Doing so does require two additional inductors, but allows smaller, less expensive inductors to be used because the current is divided between the two inductors. This process is called Post-Filter PBTL. Both variants of mono operation are shown in Figure 70 and Figure 71.

Figure 70. Pre-Filter PBTL

Figure 71. Post-Filter PBTL

On the input side of the TAS5780M device, the input signal to the mono amplifier can be selected from the any slot in a TDM stream or the left or right frame from an I²S, LJ, or RJ signal. The TAS5780M device can also be configured to amplify some mixture of two signals, as in the case of a subwoofer channel which mixes the left and right channel together and sends the mixture through a low-pass filter to create a mono, low-frequency signal.

The mono mode of operation is shown in the Mono (PBTL) Systems section.

9.4.3.3 Master and Slave Mode Clocking for Digital Serial Audio Port

The digital audio serial port in the TAS5780M device can be configured to receive clocks from another device as a serial audio slave device. The slave mode of operation is described in the Clock Slave Mode with SCLK PLL to Generate Internal Clocks (3-Wire PCM) section. If no system processor is available to provide the audio clocks, the TAS5780M device can be placed into Master Mode. In master mode, the TAS5780M device provides the clocks to the other audio devices in the system. For more details regarding the Master and Slave mode operation within the TAS5780M device, see the Serial Audio Port Operating Modes section.

9.5.2.1 Input Scale and Mixer

The input mixer can be used to mix the left and right channel input signals as shown in Figure 73. The input mixer has four coefficients, which control the mixing and gains of the input signals. When mixing and scaling the input signals, ensure that at maximum input level the input mixer outputs don't exceed 0 dBFS, which will overdrive the SRC inputs.

Figure 73. Input Scale and Mixer

9.5.2.2 Sample Rate Converter

The sample rate converter supports 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz and 96 kHz input sample rates. These input sample rates are converted to 88.2 or 96 kHz sample rate. The sample rate detection doesn’t distinguish between sample rates from 32 to 48 kHz. These sample rates are treated as 48 kHz by the sample rate converter. The detected sample rate can be read at book 0x78 page 0x0C register 0x5C. The input sample rate is 88.2 or 96 kHz at register 0x5C which reads 0x00 00 00 01. The input sample rate is 32 to 48 kHz at register 0x5C which reads 0x00 00 00 02. Input sample rate 32 kHz requires changing the interpolation setting from 2x to 3x by writing B0-P0-R37-D7 to 1. The device must be placed in standby mode for this change to take effect.

Even though the sample rate converter supports 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz and 96 kHz input sample rates, the TAS5780M device supports all input sample rates shown in Table 22 in 1x interpolation mode, base rate processing.

The SRC input should not be overdriven. Making the maximum signal level into the SRC –0.5dBFs is recommended to prevent overdriving the SRC and causing audio artifacts. The input scale and mixer can be used to attenuate or boost the maximum input signal to –0.5dBFs. The processing block has several blocks after the SRC where the signal can be compensate for any gain attenuation done in the input mixer and scale block to prevent over driving the SRC.

9.5.2.3 Parametric Equalizers (PEQ)

The device supports 12 individual tuned PEQs for left channel and 12 individual tuned PEQs for the right channel. The PEQs are implemented using cascaded “direct form 1” BQs structures as shown in Figure 74.

Figure 74. Cascaded BQ Structure

Equation 2.

All BQ coefficients are normalized with a0 to insure that a0 is equal to 1. The structure requires 5 BQ coefficients as shown in Table x. Any BQ with coefficients greater than 1 undergoes gain scaling as described in BQ Gain Scale.

9.5.2.4 BQ Gain Scale

Figure 75. PEQs and BQs Gain Scale Block

The BQ coefficients format is as follows: The first BQ has B0 = 5.x, B1 = 6.x, B2 = 5.x, A1 = 2.x, and A2 = 1.x. The rest of the BQ have this format: B0 = 1.x, B1 = 2.x, B2 = 1.x, A1 = 2.x, and A2 = 1.x. This formatting maintains the highest possible resolution and noise performance. The 1.31 format restricts the ability to do high gains within the BQs and as a result requires gain compensation for the restriction. When generating BQ coefficients, ensure none of the BQ coefficients is greater than 1 by implementing gain compensation. The Gain compensation reduces the BQ coefficients gain to ensure all BQ coefficients are less than 1. The reduced gain is then reapplied in the subsequent gain scale block.

Gain compensation takes the maximum value of B0_DSP, B1_DSP, and B2_DSP after the BQ normalization shown in Table 23 is implemented. All the B coefficients are divided by maximum B coefficient value then multiplied by 0.999999999534339 (the nearest two’s complement 32-bit number to 1). The following calculations are done for each BQ in the PEQ block:

Equation 3.

Equation 4.

Equation 5.

Equation 6.

Equation 7.

The calculations above insure all DSP BQ coefficients are in a 1.31 format. The reduced gains in the BQ 1.31 format is compensation for in the gain scale block. The following calculation is done for each channel.

The calculated k_BQ compensation value is then applied to the BQ gain scale in an 8.24 format. The BQ gain scale can also be used for volume control before the DRCs. The block can be considered as BQ gain scale and volume gain block. When the BQ gain scale block is used for volume control the coefficient value must be calculated as follows:

Equation 9.

where

• Volume is in dB

The BQ gain scale coefficients are located in book 0x8C, page 0x1F register 0x58 for left and register 0x5C for right.

The Bypass EQ Mux allows the user to bypass all processing. The Bypass EQ mux is at Page 0x21, Register 0x64. The Gang Left / Right mux forces the left processing to be the same as the right processing. The Gang Left / Right Mux is located at Page 0x21, Register 0x68.

9.5.2.5 Dynamic Parametric Equalizer (DPEQ)

The dynamic parametric equalizer mixes the audio signals routed through two paths containing one BQ each based upon the signal level detected by the sense path, as shown in Figure 76. The sense path contains one BQ, which can be used to focus the DPEQ sensing on a specific frequency bandwidth. An alpha filter structure is used to sense the energy in the sense path and setting the dynamic mixing ratios.

Figure 76. DPEQ Signal Path

The dynamic mixing is controlled by offset, gain, and alpha coefficients in a 1.31 format. The alpha coefficient controls the average time constant in ms of the signal data in the sense path. The offset and gain coefficients control the dynamic mixing thresholds shown in Figure 77.

Figure 77. Dynamic Mixing

The offset, gain and alpha coefficients are calculated as follows:

Equation 10.

Equation 11.

where

• T2 ≥ –20 dB

Equation 12.

where

• T2 < –20 dB

Equation 13.

Equation 14.

Equation 15.

where

• T1 and T2 are in dB
• The time constant is in ms

The DPEQ control coefficients are located in book 0x8C, page0x20. Register 0x58 is alpha coefficient, register 0x5C is gain coefficient and register 0x60 is offset coefficient.

The high level path BQ, low level path BQ, and sense path BQ coefficients use a 1.31 format as shown in Table 25. The DPEQ BQs don't have a gain scale to compensate for any BQ gain reduction due to the requirements of the 1.31 format. During tuning, the reduced gain can be compensated by using the BQ gain scale or the DRC offset coefficient.

The DPEQ sense gain scale is located in the sensing path. The DPEQ sense gain scale can be used to shift the dynamic mixing thresholds by changing the signal level in the sensing path. A positive dB gain shifts the dynamic mixing thresholds down by the gain amount and a negative dB gain shifts the dynamic mixing thresholds up by the gain amount.

9.5.2.6 Two-Band Dynamic Range Control

The Dynamic Range Control (DRC) is a feed-forward mechanism that can be used to automatically control the audio signal amplitude or the dynamic range within specified limits. The dynamic range control is done by sensing the audio signal level using an estimate of the alpha filter energy then adjusting the gain based on the region and slope parameters that are defined. The Dynamic Range Control is shown in Figure 78.

Figure 78. Dynamic Range Control

The DRCs have seven programmable transfer function parameters each: k0, k1, k2, T1, T2, OFF1, and OFF2. The T1 and T2 parameters specify thresholds or boundaries of the three compression or expansion regions in terms of input level. The Parameters k0, k1, and k2 define the gains or slopes of curves for each of the three regions. The parameters OFF1 and OFF2 specify the offset shift relative 1:1 transfer function curve at the thresholds T1 and T2 respectively shown in Figure 79.

Figure 79. DRC Transfer Function Example Plot

The two-band dynamic range control is comprised of two DRCs that can be spilt into two bands using the BQ at the input of each band. The frequency where the two bands are spilt is referred to as the crossover frequency. The crossover frequency is the cut off frequency for the low pass filter used to create the low band and the cut off frequency for the high pass filter used to create the high band.

Figure 80. DRC Attack and Decay

The DRC in each band is equipped with individual energy, attack, and decay time constants. The DRC time constants control the transition time of changes and decisions in the DRC gain during compression or expansion. The energy, attack, and decay time constants affect the sensitivity level of the DRC. The shorter the time constant, the more aggressive the DRC response and vice versa.

9.5.2.7 Automatic Gain Limiter

The Automatic Gain Limiter (AGL) is a feedback mechanism that can be used to automatically control the audio signal amplitude or dynamic range within specified limits. The automatic gain limiting is done by sensing the audio signal level using an alpha filter energy structure shown in Figure 82 at the output of the AGL then adjusting the gain based on the whether the signal level is above or below the defined threshold. Three decisions made by the AGL are engage, disengage, or do nothing. The rate at which the AGL engages or disengages depends on the attack and release settings, respectively.

Figure 81. AGL Transfer Function Example Plot

Figure 82. AGL Alpha Filter Structure

9.5.2.7.5 Attack Threshold

• Attack Threshold = user input level in dB

Figure 83. AGL Attack and Release

The Attack Threshold AGL coefficients are shown in .

9.5.2.8 Fine Volume

The fine volume block after the AGL can be used to provide additional fine volume steps from –192 dB to 6 dB in a 2.30 format. The Fine Coefficients are shown in .

9.5.2.9 THD Boost

A boost scalar and fine volume together can be used for clipping. The THD boost block allows the user to programmatically increase the THD by clipping at an operating point earlier than that defined by the supply rails.

9.5.2.10 Level Meter

The level meter uses an energy estimator with a programmable time constant to adjust the sensitivity level based on signal frequency and desired accuracy level. The level meter outputs of both left and right channels are written to a 32-bit sub address location in a 1.31 format as shown in . The BypassToLevelMeter Bit in Book 8C, Page 0x21, Register 0x70 can be used to switch the input to the Level Meter from the audio before processing to audio post-processing.

9.5.3.1 Number Format

The data processing path is 32 bits with 32-bit coefficients. The coefficients use the two’s complement digital number format.

9.5.4.1 Cyclic Redundancy Check (CRC) Checksum

The 8-bit CRC checksum used is the 0x7 polynomial (CRC-8-CCITT I.432.1; ATM HEC, ISDN HEC and cell delineation, (1 + x¹ + x² + x⁸). A major advantage of the CRC checksum is that it is input order sensitive.

The CRC supports all I²C transactions, excluding book and page switching. The CRC checksum is read from register 0x7E on any page of book 0x00 (B0_Page x_Reg 126). If the book isn’t Book 0, the CRC checksum is only valid on page 0x00 register 0x7E (Page 0_Reg 126). The CRC checksum can be reset by writing 0x00 00 00 00 to the same register locations where the CRC checksum is valid.

9.5.4.2 Exclusive or (XOR) Checksum

The Xor checksum is a simpler checksum scheme. It performs sequential XOR of each register byte write with the previous 8-bit checksum register value. XOR supports only YMEM, which is located in Book 0x8C and excludes page switching and all registers in Page 0x00 of Book 0x8C. XOR checksum is read from location register 0x7D on page 0x00 of book 0x8C (B140_Page 0_Reg 125). The XOR Checksum can be reset by writing 0x00 00 00 00 to the same register location where it is read.