ZHCSI79B March 2016 – May 2018 TAS5751M
PRODUCTION DATA.
Bits D2–D0: | Volume slew rate (used to control volume change and MUTE ramp rates). These bits control the number of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of the I2S data as follows: | |
Sample rate (kHz) | Approximate ramp rate | |
8/16/32 | 125 μs/step | |
11.025/22.05/44.1 | 90.7 μs/step | |
12/24/48 | 83.3 μs/step |
In two-band AGL, register 0x0A should be set to 0x30 and register 0x0E bits 6 and 5 should be set to 1.
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | FUNCTION |
---|---|---|---|---|---|---|---|---|
1 | – | – | – | – | – | – | – | Reserved(1) |
– | 0 | – | – | – | – | – | – | AGL2 volume 1 (ch4) from I2C register 0x08 |
– | 1 | – | – | – | – | – | – | AGL2 volume 1 (ch4) from I2C register 0x0A(1) |
– | – | 0 | – | – | – | – | – | AGL2 volume 2 (ch3) from I2C register 0x09 |
– | – | 1 | – | – | – | – | – | AGL2 volume 2 (ch3) from I2C register 0x0A(1) |
– | – | – | 1 | 0 | – | – | – | Reserved(1) |
– | – | – | – | – | 0 | 0 | 0 | Volume slew 512 steps (43 ms volume ramp time at 48 kHz)(1) |
– | – | – | – | – | 0 | 0 | 1 | Volume slew 1024 steps (85-ms volume ramp time at 48 kHz) |
– | – | – | – | – | 0 | 1 | 0 | Volume slew 2048 steps (171-ms volume ramp time at 48 kHz) |
– | – | – | – | – | 0 | 1 | 1 | Volume slew 256 steps (21-ms volume ramp time at 48 kHz) |
– | – | – | – | – | 1 | X | X | Reserved |