ZHCSI79B March 2016 – May 2018 TAS5751M
PRODUCTION DATA.
SUBADDRESS | REGISTER NAME | NO. OF BYTES | CONTENTS | DEFAULT
VALUE |
---|---|---|---|---|
A u indicates unused bits. | ||||
0x00 | Clock control register | 1 | Description shown in subsequent section | 0x6C |
0x01 | Device ID register | 1 | Description shown in subsequent section | 0x40 |
0x02 | Error status register | 1 | Description shown in subsequent section | 0x00 |
0x03 | System control register 1 | 1 | Description shown in subsequent section | 0xA0 |
0x04 | Serial data interface register | 1 | Description shown in subsequent section | 0x05 |
0x05 | System control register 2 | 1 | Description shown in subsequent section | 0x40 |
0x06 | Soft mute register | 1 | Description shown in subsequent section | 0x00 |
0x07 | Master volume | 2 | Description shown in subsequent section | 0x03FF (mute) |
0x08 | Channel 1 vol | 2 | Description shown in subsequent section | 0x00C0 (0 dB) |
0x09 | Channel 2 vol | 2 | Description shown in subsequent section | 0x00C0 (0 dB) |
0x0A | Channel 3 vol | 2 | Description shown in subsequent section | 0x00C0 (0 dB) |
0x0B | Reserved | 2 | Reserved(1) | 0x03FF |
0x0C | 2 | Reserved(1) | 0x00C0 | |
0x0D | 1 | Reserved(1) | 0xC0 | |
0x0E | Volume configuration register | 1 | Description shown in subsequent section | 0xF0 |
0x0F | Reserved | 1 | Reserved(1) | 0x97 |
0x10 | Modulation limit register | 1 | Description shown in subsequent section | 0x01 |
0x11 | IC delay channel 1 | 1 | Description shown in subsequent section | 0xAC |
0x12 | IC delay channel 2 | 1 | Description shown in subsequent section | 0x54 |
0x13 | IC delay channel 3 | 1 | Description shown in subsequent section | 0xAC |
0x14 | IC delay channel 4 | 1 | Description shown in subsequent section | 0x54 |
0x15 | Reserved | 1 | Reserved(1) | 0xAC |
0x16 | 0x54 | |||
0x17 | 0x00 | |||
0x18 | PWM Start | 0x0F | ||
0x19 | PWM Shutdown Group Register | 1 | Description shown in subsequent section | 0x30 |
0x1A | Start/stop period register | 1 | Description shown in subsequent section | 0x68 |
0x1B | Oscillator trim register | 1 | Description shown in subsequent section | 0x82 |
0x1C | BKND_ERR register | 1 | Description shown in subsequent section | 0x57 |
0x1D–0x1F | 1 | Reserved(1) | 0x00 | |
0x20 | Input MUX register | 4 | Description shown in subsequent section | 0x0001 7772 |
0x21 | Reserved | 4 | Reserved(1) | 0x0000 4303 |
0x22 | 4 | 0x0000 0000 | ||
0x23 | 4 | 0x0000 0000 | ||
0x24 | 4 | 0x0000 0000 | ||
0x25 | PWM MUX register | 4 | Description shown in subsequent section | 0x0102 1345 |
0x26 | ch1_bq[0] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x27 | ch1_bq[1] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x28 | ch1_bq[2] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x29 | ch1_bq[3] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x2A | ch1_bq[4] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x2B | ch1_bq[5] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x2C | ch1_bq[6] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x2D | ch1_bq[7] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x2E | ch1_bq[8] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x2F | ch1_bq[9] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x30 | ch2_bq[0] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x31 | ch2_bq[1] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x32 | ch2_bq[2] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x33 | ch2_bq[3] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x34 | ch2_bq[4] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x35 | ch2_bq[5] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x36 | ch2_bq[6] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x37 | ch2_bq[7] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x38 | ch2_bq[8] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x39 | ch2_bq[9] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x3A | Reserved | 4 | Reserved(1) | 0x0080 0000 0000 0000 |
0x3B | AGL1 softening filter alpha | 8 | u[31:26], ae[25:0] | 0x0008 0000 |
AGL1 softening filter omega | u[31:26], oe[25:0] | 0x0078 0000 | ||
0x3C | AGL1 attack rate | 8 | Description shown in subsequent section | 0x0000 0100 |
AGL1 release rate | Description shown in subsequent section | 0xFFFF FF00 | ||
0x3D | 8 | Reserved(1) | ||
0x3E | AGL2 softening filter alpha | 8 | u[31:26], ae[25:0] | 0x0008 0000 |
AGL2 softening filter omega | u[31:26], oe[25:0] | 0x0078 0000 | ||
0x3F | AGL2 attack rate | 8 | u[31:26], at[25:0] | 0x0008 0000 |
AGL2 release rate | u[31:26], rt[25:0] | 0xFFF8 0000 | ||
0x40 | AGL1 attack threshold | 4 | T1[31:0] (9.23 format) | 0x0800 0000 |
0x41 | AGL3 attack threshold | 4 | T1[31:0] (9.23 format) | 0x0074 0000 |
0x42 | AGL3 attack rate | 8 | Description shown in subsequent section | 0x0008 0000 |
AGL3 release rate | Description shown in subsequent section | 0xFFF8 0000 | ||
0x43 | AGL2 attack threshold | 4 | T2[31:0] (9.23 format) | 0x0074 0000 |
0x44 | AGL4 attack threshold | 4 | T1[31:0] (9.23 format) | 0x0074 0000 |
0x45 | AGL4 attack rate | 8 | 0x0008 0000 | |
AGL4 release rate | 0xFFF8 0000 | |||
0x46 | AGL control | 4 | Description shown in subsequent section | 0x0002 0000 |
0x47 | AGL3 softening filter alpha | 8 | u[31:26], ae[25:0] | 0x0008 0000 |
AGL3 softening filter omega | u[31:26], oe[25:0] | 0x0078 0000 | ||
0x48 | AGL4 softening filter alpha | 8 | u[31:26], ae[25:0] | 0x0008 0000 |
AGL4 softening filter omega | u[31:26], oe[25:0] | 0x0078 0000 | ||
0x49 | Reserved | 4 | Reserved(1) | |
0x4A | 4 | 0x1212 1010 E1FF FFFF F95E 1212 | ||
0x4B | 4 | 0x0000 296E | ||
0x4C | 4 | 0x0000 5395 | ||
0x4D | 4 | 0x0000 0000 | ||
0x4E | 4 | 0x0000 0000 | ||
0x4F | PWM switching rate control | 4 | u[31:4], src[3:0] | 0x0000 0008 |
0x50 | Bank switch control | 4 | Description shown in subsequent section | 0x0F70 8000 |
0x51 | Ch 1 output mixer | 12 | Ch 1 output mix1[2] | 0x0080 0000 |
Ch 1 output mix1[1] | 0x0000 0000 | |||
Ch 1 output mix1[0] | 0x0000 0000 | |||
0x52 | Ch 2 output mixer | 12 | Ch 2 output mix2[2] | 0x0080 0000 |
Ch 2 output mix2[1] | 0x0000 0000 | |||
Ch 2 output mix2[0] | 0x0000 0000 | |||
0x53 | 16 | Reserved(1) | 0x0080 0000 0000 0000 0000 0000 | |
0x54 | 16 | Reserved(1) | 0x0080 0000 0000 0000 0000 0000 | |
0x56 | Output post-scale | 4 | u[31:26], post[25:0] | 0x0080 0000 |
0x57 | Output pre-scale | 4 | u[31:26], pre[25:0] (9.17 format) | 0x0002 0000 |
0x58 | ch1_bq[10] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x59 | ch1_cross_bq[0] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
ch1_cross_bq[1] | 0x0000 0000 | |||
ch1_cross_bq[2] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x5A | ch1_cross_bq[1] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x5B | ch1_cross_bq[2] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x5C | ch1_cross_bq[3] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x5D | ch2_bq[10] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x5E | ch2_cross_bq[0] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x5F | ch2_cross_bq[1] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x60 | ch2_cross_bq[2] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x61 | ch2_cross_bq[3] | 20 | u[31:26], b0[25:0] | 0x0080 0000 |
u[31:26], b1[25:0] | 0x0000 0000 | |||
u[31:26], b2[25:0] | 0x0000 0000 | |||
u[31:26], a1[25:0] | 0x0000 0000 | |||
u[31:26], a2[25:0] | 0x0000 0000 | |||
0x62 | IDF post scale | 4 | Description shown in subsequent section | 0x0000 0080 |
0x63–0x69 | Reserved | 4 | Reserved(1) | 0x0000 0000 |
0x6A | 4 | 0x0000 8312 | ||
0x6B | Left channel PWM level meter | 4 | Data[31:0] | 0x007F 7CED |
0x6C | Right channel PWM level meter | 4 | Data[31:0] | 0x0000 0000 |
0x6D | Reserved | 8 | Reserved(1) | 0x0000 0000 0000 0000 |
0x6E–0x6F | 4 | 0x0000 0000 | ||
0x70 | ch1 inline mixer | 4 | u[31:26], in_mix1[25:0] | 0x0080 0000 |
0x71 | inline_AGL_en_mixer_ch1 | 4 | u[31:26], in_mixagl_1[25:0] | 0x0000 0000 |
0x72 | ch1 right_channel mixer | 4 | u[31:26], right_mix1[25:0] | 0x0000 0000 |
0x73 | ch1 left_channel_mixer | 4 | u[31:26], left_mix_1[25:0] | 0x0080 0000 |
0x74 | ch2 inline mixer | 4 | u[31:26], in_mix2[25:0] | 0x0080 0000 |
0x75 | inline_AGL_en_mixer_ch2 | 4 | u[31:26], in_mixagl_2[25:0] | 0x0000 0000 |
0x76 | ch2 left_chanel mixer | 4 | u[31:26], left_mix1[25:0] | 0x0000 0000 |
0x77 | ch2 right_channel_mixer | 4 | u[31:26], right_mix_1[25:0] | 0x0080 0000 |
0x78–0xF7 | Reserved(1) | 0x0000 0000 | ||
0xF8 | Update device address key | 4 | Dev Id Update Key[31:0] (Key = 0xF9A5A5A5) | 0x0000 0054 |
0xF9 | Update device address | 4 | u[31:8],New Dev Id[7:0] (New Dev Id = 0x54 for TAS5751M) | 0x0000 0054 |
0xFA–0xFF | 4 | Reserved(1) | 0x0000 0000 |
All DAP coefficients are 3.23 format unless specified otherwise.
Registers 0x3B through 0x46 should be altered only during the initialization phase.