ZHCSHK8B October 2017 – October 2018 TAS2770
During the power-up sequence, the power-on-reset circuit (POR) monitoring the AVDD pin will hold the device in reset (including all configuration registers) until the supply is valid. The device will not exit hardware shutdown until AVDD is valid and the SDZ pin is released. Once SDZ is released, the digital core voltage regulator will power up, enabling detection of the operational mode. If AVDD dips below the POR threshold, the device will immediately be forced into a reset state.
The device also monitors the VBAT supply and holds the analog core in power down if the supply is below the UVLO threshold or above the OVLO threshold. If the TAS2770 is in active operation and a UVLO or OVLO fault occurs, the analog supplies will immediately power down to protect the device. These faults are latching and require a transition through HW/SW shutdown to clear the fault. The live and latched registers will report UVLO/OVLO faults.
The device transitions into software shutdown mode if it detects any faults with the TDM clocks such as:
• Invalid SBCLK to FSYNC ratio
• Invalid FSYNC frequency
• Halting of SBCLK or FSYNC clocks
Upon detection of a TDM clock error, the device transitions into software shutdown mode as quickly as possible to limit the possibility of audio artifacts. Once all TDM clock errors are resolved, the device volume ramps back to its previous playback state. During a TDM clock error, the IRQZ pin will assert low if the clock error interrupt mask register bit is set low (INT_MASK). The clock fault is also available for readback in the live or latched fault status registers (INT_LIVE and INT_LTCH). Reading the latched fault status register (INT_LTCH[7:0]) clears the register.
The TAS2770 also monitors die temperature and Class-D load current and will enter software shutdown mode if either of these exceed safe values. As with the TDM clock error, the IRQZ pin will assert low for these faults if the appropriate fault interrupt mask register bit is set low (INT_MASK for over temp and INT_MASK for over current). The fault status can also be monitored in the live and latched fault registers as with the TDM clock error.
Die over temp and Class-D over current errors can either be latching (i.e. the device will enter software shutdown until a HW/SW shutdown sequence is applied) or they can be configured to automatically retry after a prescribed time. This behavior can be configured in the OTE_RETRY and OCE_RETRY register bits (for over temp and over current respectively). Even in latched mode, the Class-D will not attempt to retry after an over temp or over current error until the retry time period (1.5s) has elapsed. This prevents applying repeated stress to the device in a rapid fashion that could lead to device damage. If the device has been cycled through SW/HW shutdown, the device will only begin to operate after the retry time period.
The status registers (and IRQZ pin if enabled via the status mask register) also indicates limiter behavior including when the limiter is activity, when VBAT is below the inflection point, when maximum attenuation has been applied, when the limiter is in infinite hold and when the limiter has muted the audio.
The IRQZ pin is an open drain output that asserts low during unmasked fault conditions and therefore must be pulled up with a resistor to IOVDD. An internal pull up resistor is provided in the TAS2770 and can be accessed by setting the IRQZ_PU register bit high. Figure 54 below highlights the IRQZ pin circuit.
|INT_MASK[10:0] Bit||Interrupt||Default (1 = Mask)|
|0||Over Temp Error|| |
|1||Over Current Error|| |
|2||TDM Clock Error|| |
|3||Limiter Active|| |
|4||VBAT < Inf Point|| |
|5||Limiter Max Atten|| |
|6||Limiter Inf Hold|| |
|7||Limiter Mute|| |
|8||PDM Clock Error|| |
|9||VBAT Brown Out|| |
|10||VBAT UVLO|| |
|11||VBAT OVLO|| |
| ||Disabled (default)|
| ||IRQZ will assert on any unmasked live interrupts|
| ||IRQZ will assert on any unmasked latched interrupts (default)|