ZHCSBP5C september   2013  – october 2020 SN65DSI86

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 MIPI Dual DSI Interface
      2. 8.3.2 Embedded DisplayPort Interface
      3. 8.3.3 General-Purpose Input and Outputs
        1. 8.3.3.1 GPIO REFCLK and DSIA Clock Selection
        2. 8.3.3.2 Suspend Mode
        3. 8.3.3.3 Pulse Width Modulation (PWM)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset Implementation
      2. 8.4.2 Power-Up Sequence
      3. 8.4.3 Power Down Sequence
      4. 8.4.4 Display Serial Interface (DSI)
        1. 8.4.4.1 DSI Lane Merging
        2. 8.4.4.2 DSI Supported Data Types
        3. 8.4.4.3 Generic Request Datatypes
          1. 8.4.4.3.1 Generic Read Request 2-Parameters Request
          2. 8.4.4.3.2 Generic Short Write 2-Parameters Request
          3. 8.4.4.3.3 Generic Long Write Packet Request
        4. 8.4.4.4 DSI Pixel Stream Packets
        5. 8.4.4.5 DSI Video Transmission Specifications
        6. 8.4.4.6 Video Format Parameters
        7. 8.4.4.7 GPU LP-TX Clock Requirements
      5. 8.4.5 DisplayPort
        1. 8.4.5.1  HPD (Hot Plug/Unplug Detection)
        2. 8.4.5.2  AUX_CH
          1. 8.4.5.2.1 Native Aux Transactions
        3. 8.4.5.3  I2C-Over-AUX
          1. 8.4.5.3.1 Direct Method (Clock Stretching)
          2. 8.4.5.3.2 Indirect Method (CFR Read/Write)
        4. 8.4.5.4  DisplayPort PLL
        5. 8.4.5.5  DP Output VOD and Pre-emphasis Settings
        6. 8.4.5.6  DP Main Link Configurability
        7. 8.4.5.7  DP Main Link Training
          1. 8.4.5.7.1 Manual Link Training
          2. 8.4.5.7.2 Fast Link Training
          3. 8.4.5.7.3 54
          4. 8.4.5.7.4 Semi-Auto Link Training
          5. 8.4.5.7.5 Redriver Semi-Auto Link Training
        8. 8.4.5.8  Panel Size vs DP Configuration
        9. 8.4.5.9  Panel Self Refresh (PSR)
        10. 8.4.5.10 Secondary Data Packet (SDP)
        11. 8.4.5.11 Color Bar Generator
        12. 8.4.5.12 DP Pattern
          1. 8.4.5.12.1 HBR2 Compliance Eye
          2. 8.4.5.12.2 80-Bit Custom Pattern
        13. 8.4.5.13 BPP Conversion
    5. 8.5 Programming
      1. 8.5.1 Local I2C Interface Overview
    6. 8.6 Register Map
      1. 8.6.1 Standard CFR Registers (PAGE 0)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 1080p (1920x1080 60 Hz) Panel
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 eDP Design Procedure
          2. 9.2.1.2.2 76
          3. 9.2.1.2.3 DSI Design Procedure
          4. 9.2.1.2.4 78
          5. 9.2.1.2.5 Example Script
        3. 9.2.1.3 Application Curve
  11. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCCA Power supply
    3. 10.3 VPLL and VCCIO Power Supplies
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DSI Guidelines
      2. 11.1.2 eDP Guidelines
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

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6 Pin Configuration and Functions

GUID-8709B16D-ADE9-4138-B9EB-C59C097FA0A9-low.gif
See Section 11.1 for additional information.
Figure 6-1 ZXH Package64-Pin nFBGATop View
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
ADDR A1 CMOS Input/Output Local I2C interface target address select. See Table 8-4. In normal operation, this pin is an input. When the ADDR pin is programmed high, it must be tied to the same 1.8-V power rails where the SN65DSI86 VCCIO 1.8-V power rail is connected.
AUXP/N H8, H9 LVDS I/O Auxiliary-channel differential pair
DA0P/N H3, J3 LVDS Input (HS)
CMOS Input/Output (LS)		 MIPI D-PHY channel A data lane 0; data rate up to 1.5 Gbps.
DA1P/N H4, J4 LVDS Input (HS)
CMOS Input (LS)
(Failsafe)		 MIPI D-PHY channel a data lane 1; data rate up to 1.5 Gbps.
DA2P/N H6, J6 LVDS Input (HS)
CMOS Input (LS)
(Failsafe)		 MIPI D-PHY channel A data lane 2; data rate up to 1.5 Gbps
DA3P/N H7, J7 LVDS Input (HS)
CMOS Input (LS)
(Failsafe)		 MIPI D-PHY channel A data lane 3; data rate up to 1.5 Gbps.
DACP/N H5, J5 LVDS Input (HS)
CMOS Input (LS)
(Failsafe)		 MIPI D-PHY channel A clock lane; operates up to 750 MHz. Under proper conditions, this clock can be used instead of REFCLK to feed DisplayPort PLL.
DB0P/N C2, C1 LVDS Input (HS)
CMOS Input (LS)
(Failsafe)		 MIPI D-PHY channel B data lane 0; data rate up to 1.5 Gbps.
DB1P/N D2, D1 LVDS Input (HS)
CMOS Input (LS)
(Failsafe)		 MIPI D-PHY channel B data lane 1; data rate up to 1.5 Gbps.
DB2P/N F2, F1 LVDS Input (HS)
CMOS Input (LS)
(Failsafe)		 MIPI D-PHY channel B data lane 2; data rate up to 1.5 Gbps.
DB3P/N G2, G1 LVDS Input (HS)
CMOS Input (LS)
(Failsafe)		 MIPI D-PHY channel B data lane 3; data rate up to 1.5 Gbps.
DBCP/N E2, E1 LVDS Input (HS)
CMOS Input (LS)
(Failsafe)		 MIPI D-PHY channel B clock lane; operates up to 750 MHz.
EN B1 CMOS Input
(Failsafe)		 Chip enable and reset. Device is reset (shutdown) when EN is low.
Deassertion (low) of EN will cause all internal CSRs and functions to be reset to default state.
GND A8, D8, E4, E5, F4, F5, F6, G8 Power Supply Reference ground for digital and analog circuits.
GPIO[4:1] B4, A6, A5, A4 CMOS Input/Output General-purpose I/O. See Section 8.3.3 section for details on GPIO functionality.
When these pins are set high, tie the pins to the same 1.8-V power rail that the SN65DSI86 VCCIO 1.8-V power rail is connected to.
HPD J8 CMOS Input with internal pulldown.
(Failsafe)		 HPD input. This input requires a 51-kΩ 1% series resistor.
IRQ A3 CMOS Output Interrupt signal
ML0P/N F8, F9 LVDS output (DP) DisplayPort lane 0 transmit differential pair. Supports 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, and 5.4 Gbps.
All DisplayPort lanes transmit at the same data rate.
ML1P/N E8, E9 LVDS output (DP) DisplayPort lane 1 transmit differential pair. Supports 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, and 5.4 Gbps.
All DisplayPort lanes transmit at the same data rate.
ML2P/N C8, C9 LVDS output (DP) DisplayPort lane 2 transmit differential pair. Supports 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, and 5.4 Gbps.
All DisplayPort lanes transmit at the same data rate.
ML3P/N B8, B9 LVDS output (DP) DisplayPort lane 3 transmit differential pair. Supports 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, and 5.4 Gbps.
All DisplayPort lanes transmit at the same data rate.
REFCLK A7 Input Reference clock. Frequency determined by value programmed in I2C register or value of GPIO[3:1] latched at rising edge of EN. Supported frequencies are: 12 MHz, 19.2 MHz, 26 MHz, 27 MHz, and 38.4 MHz.
This pin must be tied to GND when DACP/N feeds the DisplayPort PLL
SCL H1 OpenDrain Input/Output
(Failsafe)		 Local I2C interface clock.
SDA J1 OpenDrain Input/Output
(Failsafe)		 Local I2C interface bidirectional data signal.
TEST1 B3 CMOS Input
with internal pulldown.		 Used for Texas Instruments internal use only. This pin must be left unconnected or tied to ground.
TEST2 B5 CMOS Input/Output
with internal pulldown		 Used for internal test, HBR2 compliance eye, and symbol error rate measurement pattern. For normal operation, pull down this pin to GND or leave unconnected. See Table 8-15 for information on HBR2 compliance eye and symbol error rate measurement patterns.
TEST3 B7 NA Used for Texas Instruments internal use only. This pin must be left unconnected or tied to GND through a 0.1-µF capacitor.
VCC D6, D5, J2, J9 Power Supply 1.2-V power supply for digital core
VCCA A9, G9, E6, B2, H2 Power Supply 1.2-V power supply for analog circuits.
AVCC and VCC can be applied simultaneously.
VCCIO B6, A2 Power Supply 1.8-V power supply for Digital I/O
VPLL D9 Power Supply 1.8-V power supply for DisplayPort PLL