ZHCSBP5C september   2013  – october 2020 SN65DSI86

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 MIPI Dual DSI Interface
      2. 8.3.2 Embedded DisplayPort Interface
      3. 8.3.3 General-Purpose Input and Outputs
        1. 8.3.3.1 GPIO REFCLK and DSIA Clock Selection
        2. 8.3.3.2 Suspend Mode
        3. 8.3.3.3 Pulse Width Modulation (PWM)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset Implementation
      2. 8.4.2 Power-Up Sequence
      3. 8.4.3 Power Down Sequence
      4. 8.4.4 Display Serial Interface (DSI)
        1. 8.4.4.1 DSI Lane Merging
        2. 8.4.4.2 DSI Supported Data Types
        3. 8.4.4.3 Generic Request Datatypes
          1. 8.4.4.3.1 Generic Read Request 2-Parameters Request
          2. 8.4.4.3.2 Generic Short Write 2-Parameters Request
          3. 8.4.4.3.3 Generic Long Write Packet Request
        4. 8.4.4.4 DSI Pixel Stream Packets
        5. 8.4.4.5 DSI Video Transmission Specifications
        6. 8.4.4.6 Video Format Parameters
        7. 8.4.4.7 GPU LP-TX Clock Requirements
      5. 8.4.5 DisplayPort
        1. 8.4.5.1  HPD (Hot Plug/Unplug Detection)
        2. 8.4.5.2  AUX_CH
          1. 8.4.5.2.1 Native Aux Transactions
        3. 8.4.5.3  I2C-Over-AUX
          1. 8.4.5.3.1 Direct Method (Clock Stretching)
          2. 8.4.5.3.2 Indirect Method (CFR Read/Write)
        4. 8.4.5.4  DisplayPort PLL
        5. 8.4.5.5  DP Output VOD and Pre-emphasis Settings
        6. 8.4.5.6  DP Main Link Configurability
        7. 8.4.5.7  DP Main Link Training
          1. 8.4.5.7.1 Manual Link Training
          2. 8.4.5.7.2 Fast Link Training
          3. 8.4.5.7.3 54
          4. 8.4.5.7.4 Semi-Auto Link Training
          5. 8.4.5.7.5 Redriver Semi-Auto Link Training
        8. 8.4.5.8  Panel Size vs DP Configuration
        9. 8.4.5.9  Panel Self Refresh (PSR)
        10. 8.4.5.10 Secondary Data Packet (SDP)
        11. 8.4.5.11 Color Bar Generator
        12. 8.4.5.12 DP Pattern
          1. 8.4.5.12.1 HBR2 Compliance Eye
          2. 8.4.5.12.2 80-Bit Custom Pattern
        13. 8.4.5.13 BPP Conversion
    5. 8.5 Programming
      1. 8.5.1 Local I2C Interface Overview
    6. 8.6 Register Map
      1. 8.6.1 Standard CFR Registers (PAGE 0)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 1080p (1920x1080 60 Hz) Panel
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 eDP Design Procedure
          2. 9.2.1.2.2 76
          3. 9.2.1.2.3 DSI Design Procedure
          4. 9.2.1.2.4 78
          5. 9.2.1.2.5 Example Script
        3. 9.2.1.3 Application Curve
  11. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCCA Power supply
    3. 10.3 VPLL and VCCIO Power Supplies
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DSI Guidelines
      2. 11.1.2 eDP Guidelines
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

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8.5.1 Local I2C Interface Overview

The SN65DSI86 local I2C interface is enabled when EN is input high, access to the CSR registers is supported during ultra-low power state (ULPS). The SCL and SDA terminals are used for I2C clock and I2C data, respectively. The SN65DSI86 I2C interface conforms to the two-wire serial interface defined by the I2C Bus Specification, Version 2.1 (January 2000), and supports fast mode transfers up to 400 kbps.

The device address byte is the first byte received following the START condition from the master device. The 7-bit device address for SN65DSI86 is factory preset to 010110X with the least significant bit being determined by the ADDR control input. Table 8-17 clarifies the SN65DSI86 target address.

Table 8-17 SN65DSI86 I2C Target Address Description
SN65DSI86 I2C TARGET ADDRESS
Bit 7 (MSB)Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 (W/R)
010110ADDR0/1
When ADDR = 1, Address Cycle is 0x5A (Write) and 0x5B (Read)
When ADDR = 0, Address Cycle is 0x58 (Write) and 0x59 (Read)

The following procedure is followed to write to the SN65DSI86 I2C registers:

  1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI86 7-bit address and a zero-value W/R bit to indicate a write cycle.
  2. The master presents the subaddress (I2C register within SN65DSI86) to be written, consisting of one byte of data, MSB-first.
  3. The master presents the subaddress (I2C register within SN65DSI86) to be written, consisting of one byte of data, MSB-first.
  4. The SN65DSI86 acknowledges the subaddress cycle.
  5. The master presents the first byte of data to be written to the I2C register.
  6. The SN65DSI86 acknowledges the byte transfer.
  7. The master terminates the write operation by generating a stop condition (P).
  8. The master terminates the write operation by generating a stop condition (P).

The following procedure is followed to read the SN65DSI86 I2C registers:

  1. The master initiates a read operation by generating a start condition (S), followed by the SN65DSI86 7-bit address and a one-value W/R bit to indicate a read cycle.
  2. The SN65DSI86 acknowledges the address cycle.
  3. The SN65DSI86 transmit the contents of the memory registers MSB-first starting at register 00h or last read subaddress+1. If a write to the SN65DSI86 I2C register occurred prior to the read, then the SN65DSI86 will start at the subaddress specified in the write.
  4. The SN65DSI86 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
  5. If an ACK is received, the SN65DSI86 transmits the next byte of data.
  6. The master terminates the read operation by generating a stop condition (P).

The following procedure is followed for setting a starting subaddress for I2C reads:

  1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI86 7-bit address and a zero-value W/R bit to indicate a write cycle.
  2. The SN65DSI86 acknowledges the address cycle.
  3. The master presents the subaddress (I2C register within SN65DSI86) to be written, consisting of one byte of data, MSB-first.
  4. The SN65DSI86 acknowledges the subaddress cycle.
  5. The master terminates the write operation by generating a stop condition (P).
Note:

If no subaddressing is included for the read procedure, then reads start at register offset 00h and continue byte by byte through the registers until the I2C master terminates the read operation. If a I2C write occurred prior to the read, then the reads start at the subaddress specified by the write.