ZHCSBP5C september   2013  – october 2020 SN65DSI86

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 MIPI Dual DSI Interface
      2. 8.3.2 Embedded DisplayPort Interface
      3. 8.3.3 General-Purpose Input and Outputs
        1. 8.3.3.1 GPIO REFCLK and DSIA Clock Selection
        2. 8.3.3.2 Suspend Mode
        3. 8.3.3.3 Pulse Width Modulation (PWM)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset Implementation
      2. 8.4.2 Power-Up Sequence
      3. 8.4.3 Power Down Sequence
      4. 8.4.4 Display Serial Interface (DSI)
        1. 8.4.4.1 DSI Lane Merging
        2. 8.4.4.2 DSI Supported Data Types
        3. 8.4.4.3 Generic Request Datatypes
          1. 8.4.4.3.1 Generic Read Request 2-Parameters Request
          2. 8.4.4.3.2 Generic Short Write 2-Parameters Request
          3. 8.4.4.3.3 Generic Long Write Packet Request
        4. 8.4.4.4 DSI Pixel Stream Packets
        5. 8.4.4.5 DSI Video Transmission Specifications
        6. 8.4.4.6 Video Format Parameters
        7. 8.4.4.7 GPU LP-TX Clock Requirements
      5. 8.4.5 DisplayPort
        1. 8.4.5.1  HPD (Hot Plug/Unplug Detection)
        2. 8.4.5.2  AUX_CH
          1. 8.4.5.2.1 Native Aux Transactions
        3. 8.4.5.3  I2C-Over-AUX
          1. 8.4.5.3.1 Direct Method (Clock Stretching)
          2. 8.4.5.3.2 Indirect Method (CFR Read/Write)
        4. 8.4.5.4  DisplayPort PLL
        5. 8.4.5.5  DP Output VOD and Pre-emphasis Settings
        6. 8.4.5.6  DP Main Link Configurability
        7. 8.4.5.7  DP Main Link Training
          1. 8.4.5.7.1 Manual Link Training
          2. 8.4.5.7.2 Fast Link Training
          3. 8.4.5.7.3 54
          4. 8.4.5.7.4 Semi-Auto Link Training
          5. 8.4.5.7.5 Redriver Semi-Auto Link Training
        8. 8.4.5.8  Panel Size vs DP Configuration
        9. 8.4.5.9  Panel Self Refresh (PSR)
        10. 8.4.5.10 Secondary Data Packet (SDP)
        11. 8.4.5.11 Color Bar Generator
        12. 8.4.5.12 DP Pattern
          1. 8.4.5.12.1 HBR2 Compliance Eye
          2. 8.4.5.12.2 80-Bit Custom Pattern
        13. 8.4.5.13 BPP Conversion
    5. 8.5 Programming
      1. 8.5.1 Local I2C Interface Overview
    6. 8.6 Register Map
      1. 8.6.1 Standard CFR Registers (PAGE 0)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 1080p (1920x1080 60 Hz) Panel
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 eDP Design Procedure
          2. 9.2.1.2.2 76
          3. 9.2.1.2.3 DSI Design Procedure
          4. 9.2.1.2.4 78
          5. 9.2.1.2.5 Example Script
        3. 9.2.1.3 Application Curve
  11. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCCA Power supply
    3. 10.3 VPLL and VCCIO Power Supplies
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DSI Guidelines
      2. 11.1.2 eDP Guidelines
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.6.1 Standard CFR Registers (PAGE 0)

Table 8-19 CSR Bit Field Definitions—ID Registers
ADDRESSBIT(S)DESCRIPTIONACCESS
0x00 through 0x077:0DEVICE_ID
For the SN65DSI86 these fields return a string of ASCII characters returning DSI86 preceded by three space characters.
Addresses 0x07 through 0x00 = {0x20, 0x20, 0x20, 0x44, 0x53, 0x49, 0x38, 0x36}
R
0x087:0DEVICE_REV
Device revision; returns 0x02.
Table 8-20 CSR Bit Field Definitions—Reset and Clock Registers
ADDRESSBIT(S)DESCRIPTIONACCESS
0x090SOFT_RESET
This bit automatically clears when set to 1 and returns zeros when read. This bit must be set after the CSRs are updated. This bit must also be set after making any changes to the DIS clock rate or after changing between DSI burst and non-burst modes.
0 = No action (default)
1 = Reset device to default condition excluding the CSR bits.		W
0x0A7DP_PLL_LOCK
0 = DP_PLL not locked (default)
1 = DP_PLL locked		R
6:4ReservedR
3:1REFCLK_FREQ. This field is used to control the clock source and frequency select inputs to the DP PLL. Any change in this field will cause the DP PLL to reacquire lock. On the rising edge of EN the SN65DSI86 will sample the state of GPIO[3:1] as well as detect the presence or absence of a clock on REFCLK pin. The outcome will determine whether the clock source for the DP PLL is from the REFCLK pin or the DSIA CLK. The outcome will also determine the frequency of the clock source.RWU
DPPLL_CLK_SRC = 0DPPLL_CLK_SRC = 1
000 = 12 MHz
001 = 19.2 MHz (Default)
010 = 26 MHz
011 = 27 MHz
100 = 38.4 MHz
All other combinations are 19.2 MHz		000 = Continuous DSIA CLK at 468 MHz
001 = Continuous DSIA CLK at 384 MHz
010 = Continuous DSIA CLK at 416 MHz
011 = Continuous DSIA CLK at 486 MHz
100 = Continuous DSIA CLK at 460.8 MHz
All other combinations are DSIA CLK at 384 MHz.
0DPPLL_CLK_SRC. This status field indicates the outcome of the clock detection on the REFCLK pin.
0 = Clock detected on REFCLK pin. DP_PLL clock derived from input REFCLK (default).
1 = No clock detected on REFCLK pin. DP_PLL clock derived from MIPI D-PHY channel A HS continuous clock		RU
0x0B7:0ReservedR
0x0C7:0ReservedR
0x0D0DP_PLL_EN
When this bit is set, the DP PLL is enabled
0 = PLL disabled (default)
1 = PLL enabled		RW
Table 8-21 CSR Bit Field Definitions—DSI Registers
ADDRESSBIT(S)DESCRIPTIONACCESS
0x107LEFT_RIGHT_PIXELS
This bit selects the pixel arrangement in dual-channel DSI implementations.
0 = DSI channel A receives ODD pixels and channel B receives EVEN (default)
1 = DSI channel A receives LEFT image pixels and channel B receives RIGHT image pixels		RW
6:5DSI_CHANNEL_MODE
00 = Dual-channel DSI receiver
01 = Single channel DSI receiver A (default)
10 = Reserved.
11 = Reserved		RW
4:3CHA_DSI_LANES
This field controls the number of lanes that are enabled for DSI Channel A.
00 = Four lanes are enabled
01 = Three lanes are enabled
10 = Two lanes are enabled
11 = One lane is enabled (default)
Note: Unused DSI inputs pins on the SN65DSI86 should be left unconnected.		RW
2:1CHB_DSI_LANES
This field controls the number of lanes that are enabled for DSI Channel B.
00 = Four lanes are enabled
01 = Three lanes are enabled
10 = Two lanes are enabled
11 = One lane is enabled (default)
Note: Unused DSI inputs pins on the SN65DSI86 should be left unconnected.		RW
0SOT_ERR_TOL_DIS
0 = Single bit errors are tolerated for the start of transaction SoT leader sequence (default)
1 = No SoT bit errors are tolerated		RW
0x117:6CHA_DSI_DATA_EQ
This field controls the equalization for the DSI Channel A Data Lanes
00 = No equalization (default)
01 = Reserved
10 = 1 dB equalization
11 = 2 dB equalization		RW
5:4CHB_DSI_DATA_EQ
This field controls the equalization for the DSI Channel B Data Lanes
00 = No equalization (default)
01 = Reserved
10 = 1 dB equalization
11 = 2 dB equalization		RW
3:2CHA_DSI_CLK_EQ This field controls the equalization for the DSI Channel A Clock
00 = No equalization (default)
01 = Reserved
10 = 1 dB equalization
11 = 2 dB equalization		RW
1:0CHB_DSI_CLK_EQ
This field controls the equalization for the DSI Channel A Clock
00 = No equalization (default)
01 = Reserved.
10 = 1 dB equalization
11 = 2dB equalization		RW
0x127:0CHA_DSI_CLK_RANGE
This field specifies the DSI clock frequency range in 5-MHz increments for DSI Channel A clock. The SN65DSI866 estimates the DSI clock frequency using the REFCLK frequency determined at the rising edge of EN and updates this field accordingly. Software can override this value. If the CHA_DSI_CLK_RANGE is not loaded before receiving the first DSI packet, the SN65DSI86 uses the first packet to estimate the DSI_CLK frequency and loads this field with this estimate. This first packet may not be received; thus, the host should send a first dummy packet (such as DSI read or write to register 0x00). This field may be written by the host at any time. Any non-zero value written by the host is used instead of the automatically-estimated value.
0x00 through 0x07: Reserved
0x08 = 40 ≤ frequency < 45 MHz
0x09 = 45 ≤ frequency < 50 MHz
. . .
0x96 = 750 ≤ frequency < 755 MHz
0x97 through 0xFF: Reserved		RWU
0x137:0CHB_DSI_CLK_RANGE
This field specifies the DSI clock frequency range in 5-MHz increments for DSI Channel B clock. The SN65DSI86 estimates the DSI clock frequency using the REFCLK frequency determined at the rising edge of EN and updates this field accordingly. Software can override this value. If the CHB_DSI_CLK_RANGE is not loaded before receiving the first DSI packet, the SN65DSI86 uses the first packet to estimate the DSI_CLK frequency and loads this field with this estimate. This first packet may not be received; thus, the host should send a first dummy packet (such as DSI read or write to register 0x00). This field may be written by the host at any time. Any non-zero value written by the host is used instead of the automatically-estimated value.
0x00 through 0x07: Reserved
0x08 = 40 ≤ frequency < 45 MHz
0x09 = 45 ≤ frequency < 50 MHz
. . .
0x96 = 750 ≤ frequency < 755 MHz
0x97 through 0xFF: Reserved		RWU
Table 8-22 CSR Bit Field Definitions—Video Registers
ADDRESSBIT(S)DESCRIPTIONACCESS
0x207:0CHA_ACTIVE_LINE_LENGTH_LOWRW
When the SN65DSI86 is configured for a single DSI input, this field controls the length in pixels of the active horizontal line for Channel A. When configured for Dual DSI Inputs in Odd/Even mode, this field controls the number of odd pixels in the active horizontal line that are received on DSI channel A. When configured for Dual DSI inputs in Left/Right mode, this field controls the number of left pixels in the active horizontal line that are received on DSI channel A. The value in this field is the lower 8 bits of the 12-bit value for the horizontal line length. This field defaults to 0x00.
Note: When the SN65DSI86 is configured for dual DSI inputs in Left/Right mode and LEFT_CROP field is programmed to a value other than 0x00, the CHA_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Left portion of the line after LEFT_CROP has been applied.
0x213:0CHA_ACTIVE_LINE_LENGTH_HIGHRW
When the SN65DSI86 is configured for a single DSI input, this field controls the length in pixels of the active horizontal line for Channel A. When configured for Dual DSI Inputs in Odd/Even mode, this field controls the number of odd pixels in the active horizontal line that are received on DSI channel A. When configured for Dual DSI inputs in Left/Right mode, this field controls the number of left pixels in the active horizontal line that are received on DSI channel A. The value in this field is the upper 4 bits of the 12-bit value for the horizontal line length. This field defaults to 0x00.
Note: When the SN65DSI86 is configured for dual DSI inputs in Left/Right mode and LEFT_CROP field is programmed to a value other than 0x00, the CHA_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Left portion of the line after LEFT_CROP has been applied.
0x227:0CHB_ACTIVE_LINE_LENGTH_LOWRW
When configured for Dual DSI Inputs in Odd/Even mode, this field controls the number of even pixels in the active horizontal line that are received on DSI channel B. When configured for Dual DSI inputs in Left/Right mode, this field controls the number of right pixels in the active horizontal line that are received on DSI channel B. The value in this field is the lower 8 bits of the 12-bit value for the horizontal line length. This field defaults to 0x00.
Note: When the SN65DSI86 is configured for dual DSI inputs in Left/Right mode and RIGHT_CROP field is programmed to a value other than 0x00, the CHB_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Right portion of the line after RIGHT_CROP has been applied.
0x233:0CHB_ACTIVE_LINE_LENGTH_HIGHRW
When configured for Dual DSI Inputs in Odd/Even mode, this field controls the number of even pixels in the active horizontal line that are received on DSI channel B. When configured for Dual DSI inputs in Left/Right mode, this field controls the number of right pixels in the active horizontal line that are received on DSI channel B. The value in this field is the upper 4 bits of the 12-bit value for the horizontal line length. This field defaults to 0x00.
Note: When the SN65DSI86is configured for dual DSI inputs in Left/Right mode and RIGHT_CROP field is programmed to a value other than 0x00, the CHB_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Right portion of the line after RIGHT_CROP has been applied.
0x247:0CHA_VERTICAL_DISPLAY_SIZE_LOWRW
This field controls the vertical display size in lines for Channel A. The value in this field is the lower 8 bits of the 12-bit value for the vertical display size. This field defaults to 0x00.
0x253:0CHA_VERTICAL_DISPLAY_SIZE_HIGHRW
This field controls the vertical display size in lines for Channel A. The value in this field is the upper 4 bits of the 12-bit value for the vertical display size. This field defaults to 0x00.
0x26 through 0x2B7:0ReservedR
0x2C7:0CHA_HSYNC_PULSE_WIDTH_LOWRW
This field controls the width in pixel clocks of the HSync Pulse Width for Channel A. The value in this field is the lower 8 bits of the 15-bit value for HSync Pulse width. This field defaults to 0x00.
0x2D7CHA_HSYNC_POLARITY.RW
0 = Active High Pulse. Synchronization signal is high for the sync pulse width. (default)
1 = Active Low Pulse. Synchronization signal is low for the sync pulse width.
6:0CHA_HSYNC_PULSE_WIDTH_HIGHRW
This field controls the width in pixel clocks of the HSync Pulse Width for Channel A. The value in this field is the upper 7 bits of the 15-bit value for HSync Pulse width. This field defaults to 0x00.
0x2E through 0x2F7:0Reserved.R
0x307:0CHA_VSYNC_PULSE_WIDTH_LOWRW
This field controls the length in lines of the VSync Pulse Width for Channel A. The value in this field is the lower 8 bits of the 15-bit value for VSync Pulse width. This field defaults to 0x00. The total size of the VSYNC pulse width must be at least 1 line.
0x317CHA_VSYNC_POLARITY.RW
0 = Active High Pulse. Synchronization signal is high for the sync pulse width. (Default)
1 = Active Low Pulse. Synchronization signal is low for the sync pulse width.
6:0CHA_VSYNC_PULSE_WIDTH_HIGHRW
This field controls the width in lines of the VSync Pulse Width for Channel A. The value in this field is the upper 7 bits of the 15-bit value for VSync Pulse width. This field defaults to 0x00. The total size of the VSYNC pulse width must be at least 1 line.
0x32 through 0x337:0Reserved.R
0x347:0CHA_HORIZONTAL_BACK_PORCHRW
This field controls the time in pixel clocks between the end of the HSync Pulse and the start of the active video data for Channel A. This field defaults to 0x00.
0x357:0Reserved.R
0x367:0CHA_VERTICAL_BACK_PORCHRW
This field controls the number of lines between the end of the VSync Pulse and the start of the active video data for Channel A. This field defaults to 0x00. The total size of the Vertical Back Porch must be at least 1 line.
0x377:0ReservedR
0x387:0CHA_HORIZONTAL_FRONT_PORCHRW
This field controls the time in pixel clocks between the end of the active video data and the start of the HSync Pulse for Channel A. This field defaults to 0x00.
0x397:0Reserved.R
0x3A7:0CHA_VERTICAL_FRONT_PORCHRW
This field controls the number of lines between the end of the active video data and the start of the VSync Pulse for Channel A. This field defaults to 0x00. The total size of the Vertical Front Porch must be at least 1 line.
0x3B7:0ReservedR
0x3C4COLOR_BAR_EN. When this bit is set, the SN65DSI86 generates a video test pattern on DisplayPort based on the values programmed into the Video Registers for Channel A.
0 = Transmit of SMPTE color bar disabled. (default)
1 = Transmit of SMPTE color bar enabled.		RW
3Reserved.R
2:0COLOR_BAR_PATTERN.
000 = Vertical Colors: 8 Color (Default)
001 = Vertical Colors: 8 Gray Scale
010 = Vertical Colors: 3 Color
011 = Vertical Colors: Stripes
100 = Horizontal Colors: 8 Color
101 = Horizontal Colors: 8 Gray Scale
110 = Horizontal Colors: 3 Color
111 = Horizontal Colors: Stripes		RW
0x3D7:0RIGHT_CROP. This field controls the number of pixels removed from the beginning of the active video line for DSI Channel B. This field only has meaning if the LEFT_RIGHT_PIXELS = 1. This field defaults to 0x00.RW
Note: When the SN65DSI86 is configured for dual DSI inputs in Left/Right mode and this field is programmed to a value other than 0x00, the CHB_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Right portion of the line after RIGHT_CROP has been applied.
0x3E7:0LEFT_CROP. This field controls the number of pixels removed from the end of the active video line for DSI Channel A. This field only has meaning if the LEFT_RIGHT_PIXELS = 1. This field defaults to 0x00.RW
Note: When the SN65DSI86 is configured for dual DSI inputs in Left/Right mode and this field is programmed to a value other than 0x00, the CHA_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Left portion of the line after LEFT_CROP has been applied.
Table 8-23 CSR Bit Field Definitions—DisplayPort Specific Registers
ADDRESSBIT(S)DESCRIPTIONACCESS
0x407:0MVID[7:0]RU
0x417:0MVID[15:8]RU
0x427:0MVID[23:16]RU
0x437:0NVID[7:0]RU
0x447:0NVID[15:8]RU
0x457:0NVID[23:16]RU
0x467:0Htotal[7:0]. Defaults to 0x00.RU
0x477:0Htotal[15:8]. Defaults to 0x00.RU
0x487:0Vtotal[7:0]. Defaults to 0x00.RU
0x497:0Vtotal[15:8]. Defaults to 0x00.RU
0x4A7:0Hstart[7:0]. Defaults to 0x00.RU
0x4B7:0Hstart[15:8]. Defaults to 0x00.RU
0x4C7:0Vstart[7:0]. Defaults to 0x00.RU
0x4D7:0Vstart[15:8]. Defaults to 0x00.RU
0x4E7:0HSW[7:0]. Defaults to 0x00.RU
0x4F7:0HSP_HSW[15:8]. Defaults to 0x00.RU
0x507:0VSW[7:0]. Defaults to 0x00.RU
0x517:0VSP_VSW[15:8]. Defaults to 0x00.RU
0x527:0Hwidth[7:0]. Defaults to 0x00.RU
0x537:0Hwidth[15:8]. Defaults to 0x00.RU
0x547:0Vheight[7:0]. Defaults to 0x00.RU
0x557:0Vheight[15:8]. Defaults to 0x00.RU
0x567:5MSA_MISC0_7_5. This field represents the bits per color.
000 = 6 bits per color.
001 = 8 bits per color (Default)
Others are not supported.		RU
4MSA_MISC0_4. Defaults to zero.RW
3MSA_MISC0_3. Defaults to zero.RW
2:1MSA_MISC0_2_1. This field indicates the format of the data is either RGB, YCbCr(422 or 444). The SN65DSI86 only supports RGB so this field will always be 0x0.
00 = RGB (default)		RU
0MSA_MISC0_0.
0 = Link clock and stream clock are async. (default)
1 = Link clock and stream clock are sync.		RU
0x577MSA_MISC1_7. Y-only video. The SN65DSI86 does not support this feature so this field defaults to zero.R
6:3MSA_MISC1_6_3. Reserved. Default to 0x0.R
2:1MSA_MISC1_2_1. This field is the stereo video attribute data.
00 = No 3D stereo video in-band signaling done using this field, indicating either no 3D stereo video transported or the in-band signaling done using SDP called Video Stream Configuration (VSC) packet. (Default)
01 = Next frame is Right Eye.
10 = Reserved.
11 = Next Frame is Left Eye.		RW
0MSA_MISC1_0. Default to zero.R
0x587TU_SIZE_OVERRIDE. This field is used to control whether SN65DSI86 determines Transfer Unit Size or the size is determine by the TU_SIZE field.
0 = SN65DSI86 determines TU size. (default)
1 = TU size is determined by TU_SIZE field.		RW
6:0TU_SIZE. This field is used to program the DisplayPort transfer Unit size. Valid values are between 32 (0x20) and 64 (0x40). Default is 64. When SN65DSI86 determines the TU size, the SN65DSI86 will update this register with the value determined by hardware. SN65DSI86will interpret all invalid values to be a transfer unit size of 64 (0x40).RWU
0x597:6LN3_ASSIGN. See the DP Main Link Configurability section in this document for supported logical to physical combinations based on DP_NUM_LANES.
00 = Logical Lane3 is routed to physical ML0P/N pins
01 = Logical Lane3 is routed to physical ML1P/N pins
10 = Logical Lane3 is routed to physical ML2P/N pins
11 = Logical Lane3 is routed to physical ML3P/N pins (default)		RW
5:4LN2_ASSIGN. See the DP Main Link Configurability section in this document for supported logical to physical combinations based on DP_NUM_LANES
00 = Logical Lane2 is routed to physical ML0P/N pins
01 = Logical Lane2 is routed to physical ML1P/N pins
10 = Logical Lane2 is routed to physical ML2P/N pins (default)
11 = Logical Lane2 is routed to physical ML3P/N pins.		RW
3:2LN1_ASSIGN. See the DP Main Link Configurability section in this document for supported logical to physical combinations based on DP_NUM_LANES
00 = Logical Lane1 is routed to physical ML0P/N pins
01 = Logical Lane1 is routed to physical ML1P/N pins (default)
10 = Logical Lane1 is routed to physical ML2P/N pins
11 = Logical Lane1 is routed to physical ML3P/N pins.		RW
1:0LN0_ASSIGN. See the DP Main Link Configurability section in this document for supported logical to physical combinations based on DP_NUM_LANES.
00 = Logical Lane0 is routed to physical ML0P/N pins (default)
01 = Logical Lane0 is routed to physical ML1P/N pins
10 = Logical Lane0 is routed to physical ML2P/N pins
11 = Logical Lane0 is routed to physical ML3P/N pins		RW
0x5A7ML3_POLR. When this field is set, the polarity of ML3, specified by LN3_ASSIGN, is inverted.
0 = ML3 polarity is normal (default)
1 = ML3 polarity is inverted.		RW
6ML2_POLR. When this field is set, the polarity of ML2, specified by LN2_ASSIGN, is inverted.
0 = ML2 polarity is normal (default)
1 = ML2 polarity is inverted.		RW
5ML1_POLR. When this field is set, the polarity of ML1, specified by LN1_ASSIGN, is inverted.
0 = ML1 polarity is normal (default)
1 = ML1 polarity is inverted.		RW
4ML0_POLR. When this field is set, the polarity of ML0, specified by LN0_ASSIGN, is inverted.
0 = ML0 polarity is normal (default)
1 = ML0 polarity is inverted.		RW
3VSTREAM_ENABLE. The SN65DSI86 will clear this field if the following conditions are true: Exiting SUSPEND and the PSR_EXIT_VIDEO bit is cleared.
0 = Video data from DSI is not passed to DisplayPort (default). IDLE pattern will be sent instead.
1 = Video data from DSI is passed to DisplayPort		RWU
2ENH_FRAME_ENABLE.
0 = Disable Enhanced Framing.
1 = Enable Enhanced Framing (default)		RWU
1:0ASSR_CONTROL.This field controls the scrambler seed used. Standard DP scrambler seed value is 0xFFFF. The ASSR seed value is 0xFFFF. This field is R/W if TEST2 pin is sampled high on rising edge of EN and bit 0 of offset 0x16 in Page 7 is set. Otherwise this field is read-only.
00 = Standard DP Scrambler Seed.
01 = Alternative Scrambler Seed Reset (Default).
10 = Reserved.
11 = Reserved.		R/RW
0x5B1ENCH_FRAME_PATT
0 = SR BF BF SR or BS BF BF BS (Default)
1 = SR CP CP SR or BS CP CP BS		RW
0DP_18BPP_EN. If this field is set, then 18BPP format will be transmitted over eDP interface regardless of the DSI pixel stream data type format.
0 = 24BPP RGB. (default)
1 = 18BPP RGB		RW
0x5C4HPD. Returns the state of the HPD pin after 100-ms de-bounceRU
0HPD_DISABLE
0 = HPD input is enabled. (default)
1 = HPD input is disabled		RW
Table 8-24 CSR Bit Field Definitions—GPIO Registers
ADDRESSBIT(S)DESCRIPTIONACCESS
0x5E7GPIO4_INPUT. Returns the state of the GPIO4 pin.RU
6GPIO3_INPUT. Returns the state of the GPIO3 pin.RU
5GPIO2_INPUT. Returns the state of the GPIO2 pin.RU
4GPIO1_INPUT. Returns the state of the GPIO1 pin.RU
3GPIO4_OUTPUT. When GPIO4 Control is programmed to an Output, this field will control the output level of GPIO4.
0 = GPIO4 is driven to 0 (GND). (default)
1 = GPIO4 is driven to 1.		RW
2GPIO3_OUTPUT. When GPIO3 Control is programmed to an Output, this field will control the output level of GPIO3.
0 = GPIO3 is driven to 0 (GND). (default)
1 = GPIO3 is driven to 1.		RW
1GPIO2_OUTPUT. When GPIO2 Control is programmed to an Output, this field will control the output level of GPIO3.
0 = GPIO2 is driven to 0 (GND). (default)
1 = GPIO2 is driven to 1.		RW
0GPIO1_OUTPUT. When GPIO1 Control is programmed to an Output, this field will control the output level of GPIO1.
0 = GPIO1 is driven to 0 (GND). (default)
1 = GPIO1 is driven to 1.		RW
0x5F7:6GPIO4_CTRL
00 = Input (Default)
01 = Output
10 = PWM
11 = Reserved.		RW
5:4GPIO3_CTRL
00 = Input (Default)
01 = Output
10 = DSIA HSYNC or VSYNC
11 = Reserved		RW
3:2GPI02_CTRL
00 = Input (Default)
01 = Output
10 = DSIA VSYNC
11 = Reserved		RW
1:0GPIO1_CTRL
00 = Input (Default)
01 = Output
10 = SUSPEND Input
11 = Reserved		RW
Table 8-25 CSR Bit Field Definitions—Native and I2C-Over-Aux Registers
ADDRESSBIT(S)DESCRIPTIONACCESS
0x607:1I2C_ADDR_CLAIM1. When I2C_CLAIM1_EN is enabled, the SN65DSI86 will claim I2C slave address programmed into this field. This register defaults to 0x50 which is the typical address for the EDID.RW
0I2C_CLAIM1_EN
0 = Disable (default)
1 = Enable		RW
0x617:1I2C_ADDR_CLAIM2. When I2C_CLAIM2_EN is enabled, the SN65DSI86 will claim I2C slave address programmed into this field. This register defaults to 0x30 which is the default segment pointer register.RW
0I2C_CLAIM2_EN
0 = Disable (Default)
1 = Enable		RW
0x627:1I2C_ADDR_CLAIM3. When I2C_CLAIM3_EN is enabled, the SN65DSI86 will claim I2C slave address programmed into this field. This register defaults to 0x52 which is the typical address for the EDID.RW
0I2C_CLAIM3_EN
0 = Disable (Default)
1 = Enable		RW
0x637:1I2C_ADDR_CLAIM4. When I2C_CLAIM4_EN is enabled, the SN65DSI86 will claim I2C slave address programmed into this field. This register defaults to 0x00.RW
0I2C_CLAIM4_EN
0 = Disable (Default)
1 = Enable		RW
0x64 through 0x737:0AUX_WDATA0 through AUX_WDATA15. Data to transmit. All of these registers default to 0x00.RW
0x747:4ReservedR
3:0AUX_ADDR[19:16]. This field is address bits 19 through 16 of the Native Aux 20-bit address. This field must be filled with zeros for I2C-Over-Aux transitions. This field defaults to 0x0.RW
0x757:0AUX_ADDR[15:8]. This field is bits 15 through 8 of the Native Aux 20-bit address. This field must be filled with zeros for I2C-Over-Aux request transactions. This field defaults to 0x00.RW
0x767:0AUX_ADDR[7:0]. This field is address bits 7 through 0 of the Native Aux 20-bit address. For I2C-Over-Aux request transactions this field must be the 7-bit I2C address. This field defaults to 0x00.RW
0x774:0AUX_LENGTH. Amount of Data to transmit or amount of data received. Limited to up to 16 bytes. For example, if LENGTH is 0x10, then SN65DSI86 will interpret this to mean 16 (0x10). For replies, DSIx6 will update this field with the number of bytes returned. This field defaults to 0x00.RWU
0x787:4AUX_CMD. This field is used to indicate the type of request. This field defaults to 0x00.
See Table 8-9 for request transactions codes.		RW
0SEND. When set to a 1, the SN65DSI86 will send the Native Aux request or initiate the I2C-Over_Aux transaction. SN65DSI86 will clear this bit when the request completed successfully or failed due to an error. This field defaults to 0.RSU
0x79 through 0x887:0AUX_RDATA0 through AUX_RDATA15. Data received. All of these registers default to 0x00.RU
Table 8-26 CSR Bit Field Definitions—Link Training Registers
ADDRESSBIT(S)DESCRIPTIONACCESS
0x89 through 0x927:080BIT_CUSTOM_PATTERN.
These 10 bytes represent the 80-bit Custom pattern. The default pattern is 0x1F, 0x7C, 0xF0, 0xC1, 0x07, 0x1F, 0x7C, 0xF0, 0xC1, and 0x07. In the DisplayPort PHY CTS specification this pattern is known as PLTPAT. The SN65DSI86 will continuously transmit over all enabled DisplayPort lanes starting at the LSB of data at address 0x89 through the MSB of data at address 0x92 last.		RW
0x937:6DP_PRE_EMPHASIS
This field selects the pre-emphasis setting for all DP Main Links. The actual pre-emphasis level is determined by the DP Link Training LUT registers.
00 = Pre-Emphasis Level 0 (Default)
01 = Pre-Emphasis Level 1
10 = Pre-Emphasis Level 2
11 = Pre-Emphasis Level 3		RWU
5:4DP_NUM_LANES.
00 = Not Configured. (Default)
01 = 1 DP lane.
10 = 2 DP lanes.
11 = 4 DP lanes.		RW
3:1SSC_SPREAD
000 = Down-spread 5000 ppm
001 = Down-spread 4375 ppm
010 = Down-spread 3750 ppm (default)
011 = Down-spread 3150 ppm
100 = Down-spread 2500 ppm
101 = Center-spread 3750 ppm
110 = Center-spread 4375 ppm
111 = Center-spread 5000 ppm		RW
0SSC_ENABLE
0 = Clock spread is disabled (default)
1 = Clock spread is enabled.		RW
0x947:5DP_DATARATE
000 = Not Configured (Default)
001 = 1.62 Gbps per lane (RBR)
010 = 2.16 Gbps per lane
011 = 2.43 Gbps per lane
100 = 2.70 Gbps per lane (HBR)
101 = 3.24 Gbps per lane
110 = 4.32 Gbps per lane.
111 = 5.4 Gbps per lane (HBR2)		RW
3:2DP_ERC. This field controls the edge rate for Main Link DisplayPort interface.
00 = 61 ps (default)
01 = 95 ps
10 = 122 ps
11 = 153 ps		RW
1:0DP_TX_SWING
This field selects the differential output voltage level for all DP Main Links. The actual pk-pk differential tx voltage is determined by the DP Link Training LUT registers. Note that Voltage Swing level 3 is disabled by default.
00 = Voltage Swing Level 0 (Default)
01 = Voltage Swing Level 1
10 = Voltage Swing Level 2
11 = Voltage Swing Level 3		RWU
0x957TPS1_FAST_TRAIN.
0 = TPS1 will not be transmitted in Fast Link Training Mode (Default)
1 = TPS1 will be transmitted in Fast Link Training Mode		RW
6TPS2_FAST_TRAIN
0 = TPS2 will NOT be transmitted in Fast Link Training mode (default)
1 = TPS2 will be transmitted in Fast Link Training Mode		RW
5TPS3_FAST_TRAIN
0 = TPS3 will not be used for TPS2 in Fast Link Training Mode (default)
1 = TPS3 will be used instead of TPS2 in Fast Link Training Mode.		RW
4SCRAMBLE_DISABLE
0 = Scrambling Enabled (default)
1 = Scrambling Disabled.		RW
3:1DP_POST_CURSOR2. This field contains the post cursor2 value, where PST2 = 20 × LOG(1 – 0.05 × DP_POST_CURSOR2) (in dB)
This field controls the Post Cursor2 is setting for all DP Main Links
000 = Post-Cursor2 Level 0 (0 dB) (Default)
010 = Post-Cursor2 Level 1 (0.92 dB)
100 = Post-Cursor2 Level 2 (1.94 dB)
110 = Post-Cursor2 Level 3 (3.10 dB).		RWU
0ADJUST_REQUEST_DISABLE. This field is used during Semi-Auto Link training.
0 = SN65DSI86 will read from DPCD address to determine next training level (pre-emphasis, tx swing level, and post-cursor2). (Default)
1 = SN65DSI86 will not read from DPCD address to determine next training level. It will instead go to next available Pre-emphasis level. After maximum pre-emphasis level has been reached, the SN65DSI86 will attempt next DP_TX_SWING and reset pre-emphasis level back to level 0. Post-Cursor2 is not used in this mode.		RW
0x963:0ML_TX_MODE
0000 = Main Link Off (default)
0001 = Normal mode (Idle pattern or active video)
0010 = TPS1
0011 = TPS2
0100 = TPS3
0101 = PRBS7
0110 = HBR2 Compliance Eye Pattern
0111 = Symbol Error Rate Measurement Pattern
1000 = 80-bit Custom Pattern
1001 = Fast Link Training
1010 = Semi-Auto Link Training.
1011 = Redriver Semi-Auto Link Training
All others are Reserved.		RWU
0x977:0HBR2_COMPEYEPAT_LENGTH_LOW. This field is the count of number of scrambled 0 symbols to be output for every Enhanced Framing Scrambler Reset sequence. This count includes the reset sequence. A value less than four causes scrambled 0 symbols to be output with no scrambler reset sequence. This field represents the lower 8 bits of the 16-bit HBR2_COMPEYEPAT_LENGTH register. This field defaults to 0x04.RW
0x987:0HBR2_COMPEYEPAT_LENGTH_HIGH. This field is the count of number of scrambled 0 symbols to be output for every Enhanced Framing Scrambler Reset sequence. This count includes the reset sequence. A value less than four causes scrambled 0 symbols to be output with no scrambler reset sequence. This field represents the upper 8 bits of the 16-bit HBR2_COMPEYEPAT_LENGTH register. This field defaults to 0x01.RW
0x997LINK_RATE_SET_EN. When this field is cleared, the Semi-Auto Link training will write the appropriate value (0x06 for 1.62 Gbps, 0x0A for 2.7 Gbps, or 0x14 for 5.4 Gbps) to the sink LINK_BW_SET register at DPCD address 0x00110. When this field is set, the Semi-Auto Link Training will write the value in the LINK_RATE_SET field to the sink LINK_RATE_SET register at DPCD address 0x00115. Defaults to 0.RW
2:0LINK_RATE_SET. When LINK_RATE_SET_EN bit is set, the value in this field will be written to the sink LINK_RATE_SET register at DPCD address 0x00115 during Semi-Auto Link training process. Defaults to 0x0.RW
Table 8-27 CSR Bit Field Definitions—PWM Registers
ADDRESSBIT(S)DESCRIPTIONACCESS
0xA07:0PWM_PRE_DIV
The value programmed into this field along with the value in BACKLIGHT_SCALE is used to set the PWM frequency. The PWM frequency = REFCLK / (PWM_PRE_DIV × BACKLIGHT_SCALE + 1). This field defaults to 0x01.		RW
0xA17:0BACKLIGHT_SCALE_LOW.
The digital value corresponding to the maximum possible backlight input value. Default to 0xFF. The value in this field is the lower 8 bits of the 16-bit BACKLIGHT_SCALE register.		RW
0xA27:0BACKLIGHT_SCALE_HIGH.The digital value corresponding to the maximum possible backlight input value. Default to 0xFF. The value in this field is the upper 8 bits of the 16-bit BACKLIGHT scale register.
RW
0xA37:0BACKLIGHT_LOW
Screen brightness on a scale of 0 to BACKLIGHT_SCALE. The value in this field is the lower 8 bits of the 16-bit BACKLIGHT register. Defaults to 0x00		RW
0xA47:0BACKLIGHT_HIGH
Screen brightness on a scale of 0 to BACKLIGHT_SCALE. The value in this field is the upper 8 bits of the 16-bit BACKLIGHT register. Default to 0x00. The SN65DSI86 will latch the 16-bit BACKLIGHT value on a write to this field.		RW
0xA51PWM_EN.
0 = PWM is disabled. (Default).
1 = PWM enabled.		RW
0PWM_INV. When this bit is set, the PWM output will be inverted.
0 = Normal (default)
1 = Inverted.		RW
Table 8-28 CSR Bit Field Definitions—DP Link Training LUT
ADDRESSBIT(S)DESCRIPTIONACCESS
0xB07:4V0_P0_PRE. This field contains the post1 pre-emphasis code, where the pre-emphasis setting is given by PREdB = –20 × LOG(1 – 0.05 × V0_P0_PRE) (in dB), when the DP_TX_SWING = Level 0 and DP_PRE_EMPHASIS = Level 0 are select by the training algorithm. The default value for this field is 0 (0 dB).RW
3:0V0_P0_VOD. This field contains the TX swing code, where the emphasized output pk-pk differential voltage is given by VOD = 200 + 50 × V0_P0_VOD (in mV), when the DP_TX_SWING = Level 0 and DP_PRE_EMPHASIS = Level 0 are selected by the training algorithm. The maximum supported value is 12 (800 mV). Any value greater than 12 is reserved for SN65DSI86. The default value for this field is 4 (400 mV).RW
0xB17:4V0_P1_PRE. This field contains the post1 pre-emphasis code, where the pre-emphasis setting is given by PREdB = –20 × LOG(1 – 0.05 × V0_P1_PRE) (in dB), when the DP_TX_SWING = Level 0 and DP_PRE_EMPHASIS = Level 1 are select by the training algorithm. The default value for this field is 7 (3.74 dB).RW
3:0V0_P1_VOD. This field contains the TX swing code, where the emphasized output pk-pk differential voltage is given by VOD = 200 + 50 × V0_P1_VOD (in mV), when the DP_TX_SWING = Level 0 and DP_PRE_EMPHASIS = Level 1 are selected by the training algorithm. The maximum supported value is 12 (800 mV). Any value greater than 12 is reserved for SN65DSI86. The default value for this field is 8 (600 mV).RW
0xB27:4V0_P2_PRE. This field contains the post1 pre-emphasis code, where the pre-emphasis setting is given by PREdB = –20 × LOG(1 – 0.05 × V0_P2_PRE) (in dB), when the DP_TX_SWING = Level 0 and DP_PRE_EMPHASIS = Level 2 are select by the training algorithm. The default value for this field is 10 (6.02 dB).RW
3:0V0_P2_VOD. This field contains the TX swing code, where the emphasized output pk-pk differential voltage is given by VOD = 200 + 50 × V0_P2_VOD (in mV), when the DP_TX_SWING = Level 0 and DP_PRE_EMPHASIS = Level 2 are selected by the training algorithm. The maximum supported value is 12 (800 mV). Any value greater than 12 is reserved for SN65DSI86. The default value for this field is 12 (800 mV).RW
0xB37:4V0_P3_PRE. This field contains the post1 pre-emphasis code, where the pre-emphasis setting is given by PREdB = –20 × LOG(1 – 0.05 × V0_P3_PRE) (in dB), when the DP_TX_SWING = Level 0 and DP_PRE_EMPHASIS = Level 3 are select by the training algorithm. The default value for this field is 10 (6.02 dB).RW
3:0V0_P3_VOD. This field contains the TX swing code, where the emphasized output pk-pk differential voltage is given by VOD = 200 + 50 × V0_P3_VOD (in mV), when the DP_TX_SWING = Level 0 and DP_PRE_EMPHASIS = Level 3 are selected by the training algorithm. The maximum supported value is 12 (800 mV). Any value greater than 12 is reserved for SN65DSI86. The default value for this field is 12 (800 mV).RW
0xB47:4V1_P0_PRE. This field contains the post1 pre-emphasis code, where the pre-emphasis setting is given by PREdB = –20 × LOG(1 – 0.05 × V1_P0_PRE) (in dB), when the DP_TX_SWING = Level 1 and DP_PRE_EMPHASIS = Level 0 are select by the training algorithm. The default value for this field is 0 (0 dB).RW
3:0V1_P0_VOD. This field contains the TX swing code, where the emphasized output pk-pk differential voltage is given by VOD = 200 + 50 × V1_P0_VOD (in mV), when the DP_TX_SWING = Level 1 and DP_PRE_EMPHASIS = Level 0 are selected by the training algorithm. The maximum supported value is 12 (800 mV). Any value greater than 12 is reserved for SN65DSI86 The default value for this field is 8 (600 mV).RW
0xB57:4V1_P1_PRE. This field contains the post1 pre-emphasis code, where the pre-emphasis setting is given by PREdB = –20 × LOG(1 – 0.05 × V1_P1_PRE) (in dB), when the DP_TX_SWING = Level 1 and DP_PRE_EMPHASIS = Level 1 are select by the training algorithm. The default value for this field is 6 (3.10 dB).RW
3:0V1_P1_VOD. This field contains the TX swing code, where the emphasized output pk-pk differential voltage is given by VOD = 200 + 50 × V1_P1_VOD (in mV), when the DP_TX_SWING = Level 1 and DP_PRE_EMPHASIS = Level 1 are selected by the training algorithm. The maximum supported value is 12 (800 mV). Any value greater than 12 is reserved for SN65DSI86. The default value for this field is 12 (800 mV).RW
0xB67:4V1_P2_PRE. This field contains the post1 pre-emphasis code, where the pre-emphasis setting is given by PREdB = –20 × LOG(1 – 0.05 × V1_P2_PRE) (in dB), when the DP_TX_SWING = Level 1 and DP_PRE_EMPHASIS = Level 2 are select by the training algorithm. The default value for this field is 9 (5.19 dB).RW
3:0V1_P2_VOD. This field contains the TX swing code, where the emphasized output pk-pk differential voltage is given by VOD = 200 + 50 × V1_P2_VOD (in mV), when the DP_TX_SWING = Level 1 and DP_PRE_EMPHASIS = Level 2 are selected by the training algorithm. The maximum supported value is 12 (800 mV). Any value greater than 12 is reserved for SN65DSI86. The default value for this field is 12 (800 mV).RW
0xB77:4V1_P3_PRE. This field contains the post1 pre-emphasis code, where the pre-emphasis setting is given by PREdB = –20 × LOG(1 – 0.05 × V1_P3_PRE) (in dB), when the DP_TX_SWING = Level 1 and DP_PRE_EMPHASIS = Level 3 are select by the training algorithm. The default value for this field is 9 (5.19 dB).RW
3:0V1_P3_VOD. This field contains the TX swing code, where the emphasized output pk-pk differential voltage is given by VOD = 200 + 50 × V1_P3_VOD (in mV), when the DP_TX_SWING = Level 1 and DP_PRE_EMPHASIS = Level 3 are selected by the training algorithm. The maximum supported value is 12 (800 mV). Any value greater than 12 is reserved for SN65DSI86. The default value for this field is 12 (800 mV).RW
0xB87:4V2_P0_PRE. This field contains the post1 pre-emphasis code, where the pre-emphasis setting is given by PREdB = –20 × LOG(1 – 0.05 × V2_P0_PRE) (in dB), when the DP_TX_SWING = Level 2 and DP_PRE_EMPHASIS = Level 0 are select by the training algorithm. The default value for this field is 0 (0 dB).RW
3:0V2_P0_VOD. This field contains the TX swing code, where the emphasized output pk-pk differential voltage is given by VOD = 200 + 50 × V2_P0_VOD (in mV), when the DP_TX_SWING = Level 2 and DP_PRE_EMPHASIS = Level 0 are selected by the training algorithm. The maximum supported value is 12 (800 mV). Any value greater than 12 is reserved for SN65DSI86. The default value for this field is 12 (800 mV).RW
0xB97:4V2_P1_PRE. This field contains the post1 pre-emphasis code, where the pre-emphasis setting is given by PREdB = –20 × LOG(1 – 0.05 × V2_P1_PRE) (in dB), when the DP_TX_SWING = Level 2 and DP_PRE_EMPHASIS = Level 1 are select by the training algorithm. The default value for this field is 5 (2.50 dB).RW
3:0V2_P1_VOD. This field contains the TX swing code, where the emphasized output pk-pk differential voltage is given by VOD = 200 + 50 × V2_P1_VOD (in mV), when the DP_TX_SWING = Level 2 and DP_PRE_EMPHASIS = Level 1 are selected by the training algorithm. The maximum supported value is 12 (800 mV). Any value greater than 12 is reserved for SN65DSI86. The default value for this field is 12 (800 mV).RW
0xBA7:4V2_P2_PRE. This field contains the post1 pre-emphasis code, where the pre-emphasis setting is given by PREdB = –20 × LOG(1 – 0.05 × V2_P2_PRE) (in dB), when the DP_TX_SWING = Level 2 and DP_PRE_EMPHASIS = Level 2 are select by the training algorithm. The default value for this field is 5 (2.50 dB).RW
3:0V2_P2_VOD. This field contains the TX swing code, where the emphasized output pk-pk differential voltage is given by VOD = 200 + 50 × V2_P2_VOD (in mV), when the DP_TX_SWING = Level 2 and DP_PRE_EMPHASIS = Level 2 are selected by the training algorithm. The maximum supported value is 12 (800 mV). Any value greater than 12 is reserved for SN65DSI86. The default value for this field is 12 (800 mV).RW
0xBB7:4V2_P3_PRE. This field contains the post1 pre-emphasis code, where the pre-emphasis setting is given by PREdB = –20 × LOG(1 – 0.05 × V2_P3_PRE) (in dB), when the DP_TX_SWING = Level 2 and DP_PRE_EMPHASIS = Level 3 are select by the training algorithm. The default value for this field is 5 (2.50 dB).RW
3:0V2_P3_VOD. This field contains the TX swing code, where the emphasized output pk-pk differential voltage is given by VOD = 200 + 50 × V2_P3_VOD (in mV), when the DP_TX_SWING = Level 2 and DP_PRE_EMPHASIS = Level 3 are selected by the training algorithm. The maximum supported value is 12 (800 mV). Any value greater than 12 is reserved for SN65DSI86. The default value for this field is 12 (800 mV).RW
0xBC7:4V3_P0_PRE. This field contains the post1 pre-emphasis code, where the pre-emphasis setting is given by PREdB = –20 × LOG(1 – 0.05 × V3_P0_PRE) (in dB), when the DP_TX_SWING = Level 3 and DP_PRE_EMPHASIS = Level 0 are select by the training algorithm. The default value for this field is 0 (0 dB).RW
3:0V3_P0_VOD. This field contains the TX swing code, where the emphasized output pk-pk differential voltage is given by VOD = 200 + 50 × V3_P0_VOD (in mV), when the DP_TX_SWING = Level 3 and DP_PRE_EMPHASIS = Level 0 are selected by the training algorithm. The maximum supported value is 12 (800 mV). Any value greater than 12 is reserved for SN65DSI86. The default value for this field is 12 (800 mV).RW
0xBD7:4V3_P1_PRE. This field contains the post1 pre-emphasis code, where the pre-emphasis setting is given by PREdB = –20 × LOG(1 – 0.05 × V3_P1_PRE) (in dB), when the DP_TX_SWING = Level 3 and DP_PRE_EMPHASIS = Level 1 are select by the training algorithm. The default value for this field is 0 (0 dB).RW
3:0V3_P1_VOD. This field contains the TX swing code, where the emphasized output pk-pk differential voltage is given by VOD = 200 + 50 × V3_P1_VOD (in mV), when the DP_TX_SWING = Level 3 and DP_PRE_EMPHASIS = Level 1 are selected by the training algorithm. The maximum supported value is 12 (800 mV). Any value greater than 12 is reserved for SN65DSI86. The default value for this field is 12 (800 mV).RW
0xBE7:4V3_P2_PRE. This field contains the post1 pre-emphasis code, where the pre-emphasis setting is given by PREdB = –20 × LOG(1 – 0.05 × V3_P2_PRE) (in dB), when the DP_TX_SWING = Level 3 and DP_PRE_EMPHASIS = Level 2 are select by the training algorithm. The default value for this field is 0 (0 dB).RW
3:0V3_P2_VOD. This field contains the TX swing code, where the emphasized output pk-pk differential voltage is given by VOD = 200 + 50 × V3_P2_VOD (in mV), when the DP_TX_SWING = Level 3 and DP_PRE_EMPHASIS = Level 2 are selected by the training algorithm. The maximum supported value is 12 (800 mV). Any value greater than 12 is reserved for SN65DSI86. The default value for this field is 12 (800 mV).RW
0xBF7:4V3_P3_PRE. This field contains the post1 pre-emphasis code, where the pre-emphasis setting is given by PREdB = –20 × LOG(1 – 0.05 × V3_P3_PRE) (in dB), when the DP_TX_SWING = Level 3 and DP_PRE_EMPHASIS = Level 3 are select by the training algorithm. The default value for this field is 0 (0 dB).RW
3:0V3_P3_VOD. This field contains the TX swing code, where the emphasized output pk-pk differential voltage is given by VOD = 200 + 50 × V3_P3_VOD (in mV), when the DP_TX_SWING = Level 3 and DP_PRE_EMPHASIS = Level 3 are selected by the training algorithm. The maximum supported value is 12 (800 mV). Any value greater than 12 is reserved for SN65DSI866. The default value for this field is 12 (800 mV).RW
0xC07V0_P3_PRE_EN. When this field is set V0_P3_PRE is used in training algorithm. When this field is cleared, V0_P3_PRE is not used in training algorithm. The default for this field is 0 (disabled).RW
6V0_P3_VOD_EN. When this field is set V0_P3_VOD is used in training algorithm. When this field is cleared, V0_P3_VOD is not used in training algorithm. The default for this field is 0 (disabled).RW
5V0_P2_PRE_EN. When this field is set V0_P2_PRE is used in training algorithm. When this field is cleared, V0_P2_PRE is not used in training algorithm. The default for this field is 1 (enabled).RW
4V0_P2_VOD_EN. When this field is set V0_P2_VOD is used in training algorithm. When this field is cleared, V0_P2_VOD is not used in training algorithm. The default for this field is 1 (enabled).RW
3V0_P1_PRE_EN. When this field is set V0_P1_PRE is used in training algorithm. When this field is cleared, V0_P1_PRE is not used in training algorithm. The default for this field is 1 (enabled).RW
2V0_P1_VOD_EN. When this field is set V0_P1_VOD is used in training algorithm. When this field is cleared, V0_P1_VOD is not used in training algorithm. The default for this field is 1 (enabled).RW
1V0_P0_PRE_EN. When this field is set V0_P0_PRE is used in training algorithm. When this field is cleared, V0_P0_PRE is not used in training algorithm. The default for this field is 1 (enabled).RW
0V0_P0_VOD_EN. When this field is set V0_P0_VOD is used in training algorithm. When this field is cleared, V0_P0_VOD is not used in training algorithm. The default for this field is 1 (enabled).RW
0xC17V1_P3_PRE_EN. When this field is set V1_P3_PRE is used in training algorithm. When this field is cleared, V1_P3_PRE is not used in training algorithm. The default for this field is 0 (disabled).RW
6V1_P3_VOD_EN. When this field is set V1_P3_VOD is used in training algorithm. When this field is cleared, V1_P3_VOD is not used in training algorithm. The default for this field is 0 (disabled).RW
5V1_P2_PRE_EN. When this field is set V1_P2_PRE is used in training algorithm. When this field is cleared, V1_P2_PRE is not used in training algorithm. The default for this field is 1 (enabled).RW
4V1_P2_VOD_EN. When this field is set V1_P2_VOD is used in training algorithm. When this field is cleared, V1_P2_VOD is not used in training algorithm. The default for this field is 1 (enabled).RW
3V1_P1_PRE_EN. When this field is set V1_P1_PRE is used in training algorithm. When this field is cleared, V1_P1_PRE is not used in training algorithm. The default for this field is 1 (enabled).RW
2V1_P1_VOD_EN. When this field is set V1_P1_VOD is used in training algorithm. When this field is cleared, V1_P1_VOD is not used in training algorithm. The default for this field is 1 (enabled).RW
1V1_P0_PRE_EN. When this field is set V1_P0_PRE is used in training algorithm. When this field is cleared, V1_P0_PRE is not used in training algorithm. The default for this field is 1 (enabled).RW
0V1_P0_VOD_EN. When this field is set V1_P0_VOD is used in training algorithm. When this field is cleared, V1_P0_VOD is not used in training algorithm. The default for this field is 1 (enabled).RW
0xC27V2_P3_PRE_EN. When this field is set V2_P3_PRE is used in training algorithm. When this field is cleared, V2_P3_PRE is not used in training algorithm. The default for this field is 0 (disabled).RW
6V2_P3_VOD_EN. When this field is set V2_P3_VOD is used in training algorithm. When this field is cleared, V2_P3_VOD is not used in training algorithm. The default for this field is 0 (disabled).RW
5V2_P2_PRE_EN. When this field is set V2_P2_PRE is used in training algorithm. When this field is cleared, V2_P2_PRE is not used in training algorithm. The default for this field is 0 (disabled).RW
4V2_P2_VOD_EN. When this field is set V2_P2_VOD is used in training algorithm. When this field is cleared, V2_P2_VOD is not used in training algorithm. The default for this field is 0 (disabled).RW
3V2_P1_PRE_EN. When this field is set V2_P1_PRE is used in training algorithm. When this field is cleared, V2_P1_PRE is not used in training algorithm. The default for this field is 1 (enabled).RW
2V2_P1_VOD_EN. When this field is set V2_P1_VOD is used in training algorithm. When this field is cleared, V2_P1_VOD is not used in training algorithm. The default for this field is 1 (enabled).RW
1V2_P0_PRE_EN. When this field is set V2_P0_PRE is used in training algorithm. When this field is cleared, V2_P0_PRE is not used in training algorithm. The default for this field is 1 (enabled).RW
0V2_P0_VOD_EN. When this field is set V2_P0_VOD is used in training algorithm. When this field is cleared, V2_P0_VOD is not used in training algorithm. The default for this field is 1 (enabled).RW
0xC37V3_P3_PRE_EN. When this field is set V3_P3_PRE is used in training algorithm. When this field is cleared, V3_P3_PRE is not used in training algorithm. The default for this field is 0 (disabled).RW
6V3_P3_VOD_EN. When this field is set V3_P3_VOD is used in training algorithm. When this field is cleared, V3_P3_VOD is not used in training algorithm. The default for this field is 0 (disabled).RW
5V3_P2_PRE_EN. When this field is set V3_P2_PRE is used in training algorithm. When this field is cleared, V3_P2_PRE is not used in training algorithm. The default for this field is 0 (disabled).RW
4V3_P2_VOD_EN. When this field is set V3_P2_VOD is used in training algorithm. When this field is cleared, V3_P2_VOD is not used in training algorithm. The default for this field is 0 (disabled).RW
3V3_P1_PRE_EN. When this field is set V3_P1_PRE is used in training algorithm. When this field is cleared, V3_P1_PRE is not used in training algorithm. The default for this field is 0 (disabled).RW
2V3_P1_VOD_EN. When this field is set V3_P1_VOD is used in training algorithm. When this field is cleared, V3_P1_VOD is not used in training algorithm. The default for this field is 0 (disabled).RW
1V3_P0_PRE_EN. When this field is set V3_P0_PRE is used in training algorithm. When this field is cleared, V3_P0_PRE is not used in training algorithm. The default for this field is 0 (disabled).RW
0V3_P0_VOD_EN. When this field is set V3_P0_VOD is used in training algorithm. When this field is cleared, V3_P0_VOD is not used in training algorithm. The default for this field is 0 (disabled).RW
Table 8-29 CSR Bit Field Definitions—PSR Registers
ADDRESSBIT(S)DESCRIPTIONACCESS
0xC81PSR_EXIT_VIDEO.
0 = Upon exiting SUSPEND mode, the v will transmit IDLE patterns and the VSTREAM_ENABLE bit will be cleared. GPU software is responsible for setting the VSTREAM_ENABLE bit. (default)
1 = Upon exiting SUSPEND mode, the v will transmit IDLE patterns and the VSTREAM_ENABLE bit will be set.		RW
0PSR_TRAIN. This field controls whether or not the SN65DSI86 will perform a Semi-Auto Link Training when exiting the SUSPEND mode.
0 = PSR train will be Normal Mode (idle pattern) (default)
1 = PSR train will be Semi-Auto Link Training.		RW
Table 8-30 CSR Bit Field Definitions—IRQ Enable Registers
ADDRESSBIT(S)DESCRIPTIONACCESS
0xE00IRQ_EN
When enabled by this field, the IRQ output is driven high to communicate IRQ events.
0 = IRQ output is high-impedance (default)
1 = IRQ output is driven high when a bit is set in registers 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, or 0xF5 that also has the corresponding IRQ_EN bit set to enable the interrupt condition		RW
0xE17CHA_CONTENTION_DET_EN
0 = CHA_CONTENTION_DET_ERR is masked (default)
1 = CHA_CONTENTION_DET_ERR is enabled to generate IRQ events		RW
6CHA_FALSE_CTRL_EN
0 = CHA_FALSE_CTRL_ERR is masked (default)
1 = CHA_FALSE_CTRL_ERR is enabled to generate IRQ events		RW
5CHA_TIMEOUT_EN
0 = CHA_TIMEOUT_ERR is masked (default)
1 = CHA_TIMEOUT_ERR is enabled to generate IRQ events		RW
4CHA_LP_TX_SYNC_EN
0 = CHA_LP_TX_SYNC_ERR is masked (default)
1 = CHA_LP_TX_SYNC_ERR is enabled to generate IRQ events		RW
3CHA_ESC_ENTRY_EN
0 = CHA_ESC_ENTRY_ERR is masked (default)
1 = CHA_ESC_ENTRY_ERR is enabled to generate IRQ events		RW
2CHA_EOT_SYNC_EN
0 = CHA_EOT_SYNC_ERR is masked (default)
1 = CHA_EOT_SYNC_ERR is enabled to generate IRQ events		RW
1CHA_SOT_SYNC_EN
0 = CHA_SOT_SYNC_ERR is masked (default)
1 = CHA_SOT_SYNC_ERR is enabled to generate IRQ events		RW
0CHA_SOT_BIT_EN
0 = CHA_SOT_BIT_ERR is masked (default)
1 = CHA_SOT_BIT_ERR is enabled to generate IRQ events		RW
0xE27CHA_DSI_PROTOCOL_EN
0 = CHA_DSI_PROTOCOL_ERR is masked (default)
1 = CHA_DSI_PROTOCOL_ERR is enabled to generate IRQ events		RW
6ReservedR
5CHA_INVALID_LENGTH_EN
0 = CHA_INVALID_LENGTH_ERR is masked (default)
1 = CHA_INVALID_LENGTH_ERR is enabled to generate IRQ events		RW
4Reserved.R
3CHA_DATATYPE_EN
0 = CHA_DATATYPE_ERR is masked (default)
1 = CHA_ DATATYPE_ERR is enabled to generate IRQ events		RW
2CHA_CHECKSUM_EN
0 = CHA_CHECKSUM_ERR is masked (default)
1 = CHA_CHECKSUM_ERR is enabled to generate IRQ events		RW
1CHA_UNC_ECC_EN
0 = CHA_UNC_ECC_ERR is masked (default)
1 = CHA_UNC_ECC_ERR is enabled to generate IRQ events		RW
0CHA_COR_ECC_EN
0 = CHA_COR_ECC_ERR is masked (default)
1 = CHA_COR_ECC_ERR is enabled to generate IRQ events		RW
0xE37ReservedR
6CHB_FALSE_CTRL_EN
0 = CHB_FALSE_CTRL_ERR is masked (default)
1 = CHB_FALSE_CTRL_ERR is enabled to generate IRQ events		RW
5Reserved.R
4CHB_LP_TX_SYNC_EN
0 = CHB_LP_TX_SYNC_ERR is masked (default)
1 = CHB_LP_TX_SYNC_ERR is enabled to generate IRQ events		RW
3ReservedR
2CHB_EOT_SYNC_EN
0 = CHB_EOT_SYNC_ERR is masked (default)
1 = CHB_EOT_SYNC_ERR is enabled to generate IRQ events		RW
1CHB_SOT_SYNC_EN
0 = CHB_SOT_SYNC_ERR is masked (default)
1 = CHB_SOT_SYNC_ERR is enabled to generate IRQ events		RW
0CHB_SOT_BIT_EN
0 = CHB_SOT_BIT_ERR is masked (default)
1 = CHB_SOT_BIT_ERR is enabled to generate IRQ events		RW
0xE47CHB_DSI_PROTOCOL_EN
0 = CHB_DSI_PROTOCOL_ERR is masked (default)
1 = CHB_DSI_PROTOCOL_ERR is enabled to generate IRQ events		RW
6ReservedR
5CHB_INVALID_LENGTH_EN
0 = CHB_INVALID_LENGTH_ERR is masked (default)
1 = CHB_INVALID_LENGTH_ERR is enabled to generate IRQ events		RW
4ReservedR
3CHB_DATATYPE_EN
0 = CHB_DATATYPE_ERR is masked (default)
1 = CHB_ DATATYPE_ERR is enabled to generate IRQ events		RW
2CHB_CHECKSUM_EN
0 = CHB_CHECKSUM_ERR is masked (default)
1 = CHB_CHECKSUM_ERR is enabled to generate IRQ events		RW
1CHB_UNC_ECC_EN
0 = CHB_UNC_ECC_ERR is masked (default)
1 = CHB_UNC_ECC_ERR is enabled to generate IRQ events		RW
0CHB_COR_ECC_EN
0 = CHB_COR_ECC_ERR is masked (default)
1 = CHB_COR_ECC_ERR is enabled to generate IRQ events		RW
0xE57I2C_DEFR_EN
0 = I2C_DEFR is masked (default)
1 = I2C_DEFR is enabled to generate IRQ events.		RW
6NAT_I2C_FAIL_EN.
0 = NAT_I2C_FAIL is masked. (default)
1 = NAT_I2C_FAIL is enabled to generate IRQ events.		RW
5AUX_SHORT_EN
0 = AUX_SHORT is masked. (default)
1 = AUX_SHORT is enabled to generate IRQ events.		RW
4AUX_DEFR_EN.
0 = AUX_DEFR is masked. (default)
1 = AUX_DEFR is enabled to generate IRQ events.		RW
3AUX_RPLY_TOUT_EN.
0 = AUX_RPLY_TOUT is masked (default).
1 = AUX_RPLY_TOUT is enabled to generate IRQ events.		RW
2Reserved.R
1Reserved.R
0SEND_INT_EN.
0 = SEND_INT is masked (default)
1 = SEND_INT is enabled to generate IRQ events.		RW
0xE67ReservedRW
6ReservedRW
5PLL_UNLOCK_EN
0 = PLL_UNLOCK is masked (default)
1 = PLL_UNLOCK is enabled to generate IRQ events		RW
4ReservedRW
3HPD_REPLUG_EN.
0 = HPD_REPLUG is masked (default)
1 = HPD_REPLUG is enabled to generate IRQ events		RW
2HPD_REMOVAL _EN
0 = HPD_REMOVAL is masked. (default)
1 = HPD_REMOVAL is enabled to generate IRQ events.		RW
1HPD_INSERTION_EN
0 = HPD_INSERTION is masked. (default)
1 = HPD_INSERTION is enabled to generate IRQ events.		RW
0IRQ_HPD_EN
0 = IRQ_HPD is masked. (default)
1 = IRQ_HPD is enabled to generate IRQ events.		RW
0xE77DPTL_VIDEO_WIDTH_PROG_ERR_EN
0 = DPTL_VIDEO_WIDTH_PROG_ERR is masked. (default)
1 = DPTL_VIDEO_WIDTH_PROG_ERR is enabled to generate IRQ events.		RW
6DPTL_LOSS_OF_DP_SYNC_LOCK_EN
0 = DPTL_LOSS_OF_DP_SYNC_LOCK_ERR is masked. (default)
1 = DPTL_LOSS_OF_DP_SYNC_LOCK_ERR is enabled to generate IRQ events.		RW
5DPTL_UNEXPECTED_DATA_EN
0 = DPTL_UNEXPECTED_DATA_ERR is masked. (default)
1 = DPTL_UNEXPECTED_DATA_ERR is enabled to generate IRQ events.		RW
4DPTL_UNEXPECTED_SECDATA_EN
0 = DPTL_UNEXPECTED_SECDATA_ERR is masked. (default)
1 = DPTL_UNEXPECTED_SECDATA_ERR is enabled to generate IRQ events.		RW
3DPTL_UNEXPECTED_DATA_END_EN
0 = DPTL_UNEXPECTED_DATA_END_ERR is masked. (default)
1 = DPTL_UNEXPECTED_DATA_END_ERR is enabled to generate IRQ events.		RW
2DPTL_UNEXPECTED_PIXEL_DATA_EN
0 = DPTL_UNEXPECTED_PIXEL_DATA_ERR is masked. (default)
1 = DPTL_UNEXPECTED_PIXEL_DATA_ERR is enabled to generate IRQ events.		RW
1DPTL_UNEXPECTED_HSYNC_EN
0 = DPTL_UNEXPECTED_HSYNC_ERR is masked. (default)
1 = DPTL_UNEXPECTED_HSYNC_ERR is enabled to generate IRQ events.		RW
0DPTL_UNEXPECTED_VSYNC_EN
0 = DPTL_UNEXPECTED_VSYNC_ERR is masked. (default)
1 = DPTL_UNEXPECTED_VSYNC_ERR is enabled to generate IRQ events.		RW
0xE87ReservedRW
1DPTL_SECONDARY_DATA_PACKET_PROG_ERR_EN.
0 = DPTL_SECONDARY_DATA_PACKET_PROG_ERR is masked. (default)
1 = DPTL_SECONDARY_DATA_PACKET_PROG_ERR is enabled to generate IRQ events.		RW
0DPTL_DATA_UNDERRUN_EN
0 = DPTL_DATA_UNDERRUN_ERR is masked. (default)
1 = DPTL_DATA_UNDERRUN_ERR is enabled to generate IRQ events.		RW
0xE97:6Reserved.
5LT_EQ_CR_ERR_EN.
0 = LT_EQ_CR_ERR is masked (default)
1 = LT_EQ_CR_ERR is enabled to generate IRQ events.		RW
4LT_EQ_LPCNT_ERR_EN.
0 = LT_EQ_LPCNT_ERR is masked (default)
1 = LT_EQ_LPCNT_ERR is enabled to generate IRQ events.		RW
3LT_CR_MAXVOD_ERR_EN.
0 = LT_CR_MAXVOD_ERR is masked (default)
1 = LT_CR_MAXVOD_ERR is enabled to generate IRQ events.		RW
2LT_CR_LPCNT_ERR_EN.
0 = LT_CR_LPCNT_ERR is masked (default)
1 = LT_CR_LPCNT_ERR is enabled to generate IRQ events.		RW
1LT_FAIL_EN.
0 = LT_FAIL is masked (default)
1 = LT_FAIL is enabled to generate IRQ events.		RW
0LT_PASS_EN.
0 = LT_PASS is masked (default)
1 = LT_PASS is enabled to generate IRQ events.		RW
Table 8-31 CSR Bit Field Definitions—IRQ Status Registers
ADDRESSBIT(S)DESCRIPTIONACCESS
0xF07CHA_CONTENTION_DET_ERR. When LP high or LP low fault is detected on the DSI channel A interface, this bit is set; this bit is cleared by writing a 1 or when the SN65DSI86 responds to a Generic read/write request or unsolicited BTA with a Acknowledge and Error Report.RCU
6CHA_FALSE_CTRL_ERR. When the DSI channel A packet processor detects a LP Request not followed by the remainder of a valid escape or turnaround sequence or if it detects a HS request not followed by a bridge state (LP-00), this bit is set; this bit is cleared by writing a 1 or when the SN65DSI86 responds to a Generic read/write request or unsolicited BTA with a Acknowledge and Error Report.RCU
5CHA_TIMEOUT_ERR. When the HS Rx Timer or the LP TX timer expires, this bit is set; this bit is cleared by writing a 1 or when the DSN65DSI86 responds to a Generic read/write request or unsolicited BTA with a Acknowledge and Error Report.RCU
4CHA_LP_TX_SYNC_ERR. When the DSI channel A packet processor detects data not synchronized to a byte boundary at the end of Low-Power transmission, this bit is set; this bit is cleared by writing a 1 or when the SN65DSI86 responds to a Generic read/write request or unsolicited BTA with a Acknowledge and Error Report.RCU
3CHA_ESC_ENTRY_ERR. When the DSI Channel A packet processor detects an unrecognized Escape Mode Entry Command, this bit is set; this bit is cleared by writing a 1 or when the SN65DSI86 responds to a Generic read request or unsolicited BTA with a Acknowledge and Error Report.RCU
2CHA_EOT_SYNC_ERR. When the DSI channel A packet processor detects that the last byte of a HS transmission does not match a byte boundary, this bit is set; this bit is cleared by writing a 1 or when the SN65DSI86 responds to a Generic read/write request or unsolicited BTA with a Acknowledge and Error Report.RCU
1CHA_SOT_SYNC_ERR. When the DSI channel A packet processor detects a corrupted SOT in a way that proper synchronization cannot be expected, this bit is set; this bit is cleared by writing a 1 or when the SN65DSI86 responds to a Generic read/write request or unsolicited BTA with a Acknowledge and Error Report.RCU
0CHA_SOT_BIT_ERR When the DSI channel A packet processor detects an SoT leader sequence bit error, this bit is set; this bit is cleared by writing a 1 or when the SN65DSI86 responds to a Generic read/write request or unsolicited BTA with a Acknowledge and Error Report.RCU
0xF17CHA_DSI_PROTOCOL_ERR. When the DSI channel A packet processor detects a DSI protocol error, this bit is set; this bit is cleared by writing a 1 or when the SN65DSI86 responds to a Generic read/write request or unsolicited BTA with a Acknowledge and Error Report.RCU
6Reserved.R
5CHA_INVALID_LENGTH_ERR. When the DSI channel A packet processor detects an invalid transmission length, this bit is set; this bit is cleared by writing a 1 or when the SN65DSI86 responds to a Generic read/write request or unsolicited BTA with a Acknowledge and Error Report.RCU
4Reserved.R
3CHA_DATATYPE_ERR. When the DSI channel A packet processor detects a unrecognized DSI data type, this bit is set; this bit is cleared by writing a 1 or when the SN65DSI86 responds to a Generic read/write request or unsolicited BTA with a Acknowledge and Error Report.RCU
2CHA_CHECKSUM_ERR When the DSI channel A packet processor detects a data stream CRC error, this bit is set; this bit is cleared by writing a 1 or when the SN65DSI86 responds to a Generic read/write request or unsolicited BTA with a Acknowledge and Error Report.RCU
1CHA_UNC_ECC_ERR When the DSI channel A packet processor detects an uncorrectable ECC error, this bit is set; this bit is cleared by writing a 1 or when the SN65DSI86 responds to a Generic read/write request or unsolicited BTA with a Acknowledge and Error Report.RCU
0CHA_COR_ECC_ERR When the DSI channel A packet processor detects a correctable ECC error, this bit is set; this bit is cleared by writing a 1 or when the SN65DSI86 responds to a Generic read/write request or unsolicited BTA with a Acknowledge and Error Report.RCU
0xF27ReservedR
6CHB_FALSE_CTRL_ERR. When the DSI channel B packet processor detects a LP Request not followed by the remainder of a valid escape or turnaround sequence or if it detects a HS request not followed by a bridge state (LP-00), this bit is set; this bit is cleared by writing a 1.RCU
5ReservedR
4CHB_LP_TX_SYNC_ERR. When the DSI channel B packet processor detects data not synchronized to a byte boundary at the end of Low-Power transmission, this bit is set; this bit is cleared by writing a 1.RCU
3ReservedR
2CHB_EOT_SYNC_ERR. When the DSI channel B packet processor detects that the last byte of a HS transmission does not match a byte boundary, this bit is set; this bit is cleared by writing a 1.RCU
1CHB_SOT_SYNC_ERR. When the DSI channel B packet processor detects a corrupted SOT in a way that proper synchronization cannot be expected, this bit is set; this bit is cleared by writing a 1.RCU
0CHB_SOT_BIT_ERR When the DSI channel B packet processor detects an SoT leader sequence bit error, this bit is set; this bit is cleared by writing a 1.RCU
0xF37CHB_DSI_PROTOCOL_ERR. When the DSI channel B packet processor detects a DSI protocol error, this bit is set; this bit is cleared by writing a 1.RCU
6Reserved.R
5CHB_INVALID_LENGTH_ERR. When the DSI channel B packet processor detects an invalid transmission length, this bit is set; this bit is cleared by writing a 1.RCU
4Reserved.R
3CHB_DATATYPE_ERR. When the DSI channel B packet processor detects a unrecognized DSI data type, this bit is set; this bit is cleared by writing a 1.RCU
2CHB_CHECKSUM_ERR When the DSI channel B packet processor detects a data stream CRC error, this bit is set; this bit is cleared by writing a 1.RCU
1CHB_UNC_ECC_ERR When the DSI channel B packet processor detects an uncorrectable ECC error, this bit is set; this bit is cleared by writing a 1.RCU
0CHB_COR_ECC_ERR When the DSI channel B packet processor detects a correctable ECC error, this bit is set; this bit is cleared by writing a 1.RCU
0xF47I2C_DEFR. This field is set if an I2C-Over-Aux request has received a specific number X of I2C_DEFER from Sink. For direct method (clock stretching), the number X is 44. For indirect method, the number X is:
44 for AUX_LENGTH = 1
66 for AUX_LENGTH = 2
110 for 2 < AUX_LENGTH ≤ 4
154 for 4 < AUX_LENGTH ≤ 6
198 for 6< AUX_LENGTH ≤ 8
287 for 8< AUX_LENGTH ≤ 12
375 for 12 < AUX_LENGTH ≤ 16		RCU
6NAT_I2C_FAIL. This bit is set if the I2C-Over-Aux or Native AUX failed.RCU
5AUX_SHORT. If set, then the bytes written or received did not match requested Length. SW should read AUX_LENGTH field to determine the amount of data written or read.RCU
4AUX_DEFR. The SN65DSI86 will attempt to complete an AUX request by retrying the request seven times. This field is set if the response to the last retry is an AUX_DEFER.RCU
3AUX_RPLY_TOUT. The SN65DSI86 will attempt to complete an AUX request by retrying the request seven times. This field is set if the response to the last retry is a 400-µs timeout.RCU
2Reserved.R
1Reserved.R
0SEND_INT. This field is set whenever the SEND bit transitions from 1 to 0.RCU
0xF57ReservedRCU
6ReservedRCU
5PLL_UNLOCK This bit is set whenever the PLL Lock status transitions from LOCK to UNLOCK.RCU
4ReservedRCU
3HPD_REPLUG. This field is set whenever the SN65DSI86 detects a replug event on the HPD pin.RCU
2HPD_REMOVAL. This field is set whenever the SN65DSI86 detects a DisplayPort device removal.RCU
1HPD_INSERTION. This field is set whenever the SN65DSI86 detects a DisplayPort device insertion.RCU
0IRQ_HPD. This field is set whenever the SN65DSI86 detects a IRQ_HPD event.RCU
0xF67VIDEO_WIDTH_PROG_ERR. This field is set whenever the video parameters define more bytes of pixel data than can be transferred in the allotted video portion of the line time.RCU
6LOSS_OF_DP_SYNC_LOCK_ERR. This field is set whenever the DP sync generator has lost lock with the DSI sync stream.RCU
5DPTL_UNEXPECTED_DATA_ERR. This field is set whenever a data token at in the video stream from DSI was found at an invalid time syntactically.RCU
4DPTL_UNEXPECTED_SECDATA_ERR. This field is set whenever a secondary data start token at in the video stream was found at an invalid time syntactically.RCU
3DPTL_UNEXPECTED_DATA_END_ERR. This field is set whenever a data end token at in the video stream from DSI was found at an invalid time syntactically.RCU
2DPTL_UNEXPECTED_PIXEL_DATA_ERR. This field is set whenever a video data start token at in the video stream from DSI was found at an invalid time syntactically.RCU
1DPTL_UNEXPECTED_HSYNC_ERR. This field is set whenever a horizontal sync token at in the video stream from DSI was found at an invalid time syntactically.RCU
0DPTL_UNEXPECTED_VSYNC_ERR. This field is set whenever a vertical sync token at in the video stream from DSI was found at an invalid time syntactically.RCU
0xF77ReservedRCU
1DPTL_SECONDARY_DATA_PACKET_PROG_ERR. This field is set whenever a secondary data packet has an invalid length.RCU
0DPTL_DATA_UNDERRUN_ERR. This field is set whenever no data was received when data should have been ready.RCU
0xF87:6Reserved.R
5LT_EQ_CR_ERR. This field is set whenever link training fails in the channel equalization phase due to LANEx_CR_DONE not set.RCU
4LT_EQ_LPCNT_ERR. This field is set whenever link training fails in the channel equalization phase due to the loop count being greater than five.RCU
3LT_CR_MAXVOD_ERR. This field is set whenever link training fails in clock recovery phase due to maximum VOD reached without LANEx_CR_DONE bit(s) getting set.RCU
2LT_CR_LPCNT_ERR. This field is set whenever link training fails in the clock recovery phase due to same VOD being used five times.RCU
1LT_FAIL. This field is set whenever the Semi-Auto link training fails to train the DisplayPort Link.RCU
0LT_PASS. This field is set whenever the Semi-Auto link training successfully trains the DisplayPort Link.RCU
Table 8-32 Page Select Register
ADDRESSBIT(S)DESCRIPTIONACCESS
0xFF2:0PAGE_SELECT. This field is used to select a different page of 254 bytes. This register will reside in the same location for each Page. This register is independently controlled by either DSI or I2C. This means the value written or read by I2C does not affect the value written or read by DSI, or vice-versa. The SN65DSI86 can only access Page 0 and Page 7.
000 = Standard CFR registers. (Default)

111 = TI Test Registers.		RW
Table 8-33 Page 7
ADDRESSBIT(S)DESCRIPTIONACCESS
0x160ASSR_OVERRIDE.
0 = ASSR_CONTROL is read-only. (Default)
1 = ASSR_CONTROL is read/write.		RW