ZHCSBP5C september   2013  – october 2020 SN65DSI86

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 MIPI Dual DSI Interface
      2. 8.3.2 Embedded DisplayPort Interface
      3. 8.3.3 General-Purpose Input and Outputs
        1. 8.3.3.1 GPIO REFCLK and DSIA Clock Selection
        2. 8.3.3.2 Suspend Mode
        3. 8.3.3.3 Pulse Width Modulation (PWM)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset Implementation
      2. 8.4.2 Power-Up Sequence
      3. 8.4.3 Power Down Sequence
      4. 8.4.4 Display Serial Interface (DSI)
        1. 8.4.4.1 DSI Lane Merging
        2. 8.4.4.2 DSI Supported Data Types
        3. 8.4.4.3 Generic Request Datatypes
          1. 8.4.4.3.1 Generic Read Request 2-Parameters Request
          2. 8.4.4.3.2 Generic Short Write 2-Parameters Request
          3. 8.4.4.3.3 Generic Long Write Packet Request
        4. 8.4.4.4 DSI Pixel Stream Packets
        5. 8.4.4.5 DSI Video Transmission Specifications
        6. 8.4.4.6 Video Format Parameters
        7. 8.4.4.7 GPU LP-TX Clock Requirements
      5. 8.4.5 DisplayPort
        1. 8.4.5.1  HPD (Hot Plug/Unplug Detection)
        2. 8.4.5.2  AUX_CH
          1. 8.4.5.2.1 Native Aux Transactions
        3. 8.4.5.3  I2C-Over-AUX
          1. 8.4.5.3.1 Direct Method (Clock Stretching)
          2. 8.4.5.3.2 Indirect Method (CFR Read/Write)
        4. 8.4.5.4  DisplayPort PLL
        5. 8.4.5.5  DP Output VOD and Pre-emphasis Settings
        6. 8.4.5.6  DP Main Link Configurability
        7. 8.4.5.7  DP Main Link Training
          1. 8.4.5.7.1 Manual Link Training
          2. 8.4.5.7.2 Fast Link Training
          3. 8.4.5.7.3 54
          4. 8.4.5.7.4 Semi-Auto Link Training
          5. 8.4.5.7.5 Redriver Semi-Auto Link Training
        8. 8.4.5.8  Panel Size vs DP Configuration
        9. 8.4.5.9  Panel Self Refresh (PSR)
        10. 8.4.5.10 Secondary Data Packet (SDP)
        11. 8.4.5.11 Color Bar Generator
        12. 8.4.5.12 DP Pattern
          1. 8.4.5.12.1 HBR2 Compliance Eye
          2. 8.4.5.12.2 80-Bit Custom Pattern
        13. 8.4.5.13 BPP Conversion
    5. 8.5 Programming
      1. 8.5.1 Local I2C Interface Overview
    6. 8.6 Register Map
      1. 8.6.1 Standard CFR Registers (PAGE 0)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 1080p (1920x1080 60 Hz) Panel
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 eDP Design Procedure
          2. 9.2.1.2.2 76
          3. 9.2.1.2.3 DSI Design Procedure
          4. 9.2.1.2.4 78
          5. 9.2.1.2.5 Example Script
        3. 9.2.1.3 Application Curve
  11. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCCA Power supply
    3. 10.3 VPLL and VCCIO Power Supplies
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DSI Guidelines
      2. 11.1.2 eDP Guidelines
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 Revision History

Changes from Revision B (March 2017) to Revision C (October 2020)

  • 注：采用 MicroStar Jr. BGA 封装的器件采用层压 nFBGA 封装进行了重新设计。这种 nFBGA 封装提供了类似于数据表中的电气性能。该封装占用空间也类似于 MicroStar Jr. BGA。将在整个数据表中更新全新封装标识符来代替已停止使用的封装标识符。Go
  • 将 u*jr ZQE 更改为 nFBGA ZXHGo
  • Changed u*jr ZQE to nFBGA ZXHGo
  • Changed u*jr ZQE to nFBGA ZXH. Updated thermal information.Go

Changes from Revision A (November 2015) to Revision B (March 2017)

  • 删除了数据表中的 SN65DSI96 器件型号Go
  • 删除了特性“自适应内容管理和背光 PWM 控制...”Go
  • 添加了特性：I2C 可配置Go
  • 更新了应用 列表Go
  • 更换了简单方框图Go
  • Changed SN65DSIx6 To: SN65DSI86 throughout the data sheetGo
  • Deleted pagraph "For the SN65DSI96, the brightness is controlled.." from the Pulse Width Modulation (PWM) sectionGo
  • Deleted the PWM Backlight Selection Options table Go
  • Deleted the Assertive Display (SN65DSI96 Only) sectionGo
  • Deleted step: "Configure Assertive Display Core. (For SN65DSI96 only)" from the Power-Up Sequence sectionGo
  • Deleted step: "For SN65DSI96, disable Assertive Display core by clearing the ADEN bit." from the Power Down Sequence sectionGo
  • Changed Figure 8-11 Go
  • Deleted SN65DSI96 from address 0x00 through 0x07 of Table 8-19 Go
  • Deleted address 0x3F from the Table 8-22 Go
  • Deleted "This register is also used for SN65DSI96 when OPTION_SELECT is not equal to zero." from address 0xA3 in Table 8-27 Go
  • Deleted "This register is also used for SN65DSI96 when OPTION_SELECT is not equal to zero." from address 0xA4 in Table 8-27 Go
  • Changed 0xE6 Bits 7, 6, and 4 to Reserved in Table 8-30 Go
  • Changed 0xE8 Bits 7 to Reserved in Table 8-30 Go
  • Changed 0xF5 Bits 7, 6, and 4 to Reserved in Table 8-31 Go
  • Changed 0xF7 Bits 7 to Reserved in Table 8-31 Go
  • Deleted options 001 to 110 for 0xFF Bit 2:0 in Table 8-32 Go

Changes from Revision * (September 2013) to Revision A (November 2015)

  • 添加了引脚配置和功能 部分、ESD 等级 表、特性说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分Go
  • Changed RθJC(top) MIN value in Thermal Information table from 32.9 to 32.1Go
  • Added RθJA parameter to Thermal Information tableGo
  • Changed Description for ADDRESS 0x5A BIT(S) 1:0 from 'Reserved' to 'ASSR_CONTROL' with Bit assignments of 00, 01, 10, and 11 in Table 8-23.Go
  • Added Table 8-33 in Standard CFR Registers Go