ZHCSFS0A December 2016 – June 2018 SN65DSI83-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | CHA_REVERSE_LVDS | Reserved | CHA_LVDS_TERM | Reserved | |||
R | R/W | R | R/W | R |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | Reserved | R | Reserved. Do not write to this filed. Must remain at default. | |
5 | CHA_REVERSE_LVDS | R/W | 0 | This bit controls the order of the LVDS pins for Channel A.
0 – Normal LVDS Channel A pin order. LVDS Channel A pin order is the same as listed in the Terminal Assignments Section. (default) 1 – Reversed LVDS Channel A pin order. LVDS Channel A pin order is remapped as follows:
|
4-2 | Reserved | R | Reserved. Do not write to this filed. Must remain at default. | |
1 | CHA_LVDS_TERM | R/W | 1 | This bit controls the near end differential termination for LVDS Channel A. This bit also affects the output voltage for LVDS Channel A.
0 – 100Ω differential termination 1 – 200Ω differential termination (default) |
0 | Reserved | R | Reserved. Do not write to this filed. Must remain at default. |