ZHCSFS0A December 2016 – June 2018 SN65DSI83-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | CHA_DSI_LANES | Reserved | SOT_ERR_TOL_DIS | ||||
R | R/W | R |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | Reserved | R | Reserved | |
4-3 | CHA_DSI_LANES | R/W | 11 | This field controls the number of lanes that are enabled for DSI Channel A.
00 – Four lanes are enabled 01 – Three lanes are enabled 10 – Two lanes are enabled 11 – One lane is enabled (default) Note: Unused DSI input pins on the SN65DSI83-Q1 should be left unconnected. |
2-1 | Reserved | R | Reserved | |
0 | SOT_ERR_TOL_DIS | R/W | 0 | 0 – Single bit errors are tolerated for the start of transaction SoT leader sequence (default)
1 – No SoT bit errors are tolerated |