ZHCSFS0A December 2016 – June 2018 SN65DSI83-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | SOFT_RESET | ||||||
R | W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | Reserved | R | Reserved | |
0 | SOFT_RESET | W | 0 | This bit automatically clears when set to ‘1’ and returns zeros when read. This bit must be set after the CSR’s are updated. This bit must also be set after making any changes to the DIS clock rate or after changing between DSI burst and non-burst modes.
0 – No action (default) 1 – Reset device to default condition excluding the CSR bits. |