ZHCSK39C August   2019  – August 2020 OPA862

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VS = ±2.5 V to ±5 V
    6. 6.6 Typical Characteristics: VS = ±5 V
    7. 6.7 Typical Characteristics: VS = ±2.5 V
    8. 6.8 Typical Characteristics: VS = 1.9 V, –1.4 V
    9. 6.9 Typical Characteristics: VS = 1.9 V, –1.4 V to ±5 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and ESD Protection
      2. 7.3.2 Anti-Phase Reversal Protection
      3. 7.3.3 Precision and Low Noise
    4. 7.4 Device Functional Modes
      1. 7.4.1 Split-Supply Operation (±1.5 V to ±6.3 V)
      2. 7.4.2 Single-Supply Operation (3 V to 12.6 V)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Single-Ended-to-Differential Gain of 4 V/V
    2. 8.2 Typical Applications
      1. 8.2.1 Single-Ended to Differential with 2.5-V Output Common-Mode Voltage
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Transimpedance Amplifier Configuration
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 DC Level-Shifting
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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订购信息

8.2.1.2 Detailed Design Procedure

For RF = 0 Ω, with the VFB pin shorted to VOUT+, use Equation 3 to determine that the OPA862 is in a differential gain of 2 V/V configuration. Equation 4 describes how setting VREF equal to 2.5 V results in a VOCM of 2.5 V, as required per the design criteria. When designing a front-end stage with the OPA862, the input common-mode voltage and the output voltage range of the input and output pins, respectively, must be considered carefully. Choose the supplies such that none of these voltage ranges are violated and that the single-ended output voltages at each output do not exceed the maximum allowed voltages of the subsequent stage that the OPA862 is driving. Simulate the transfer characteristics of this circuit to ensure the output voltages are within the desired operation limits. Figure 8-3 illustrates the transfer characteristics for the OPA862 configuration in Figure 8-2. The output waveforms of the circuit in Figure 8-2 are described in Figure 8-4 and meets the design requirements of Table 8-1.