ZHCSCK8G May 2014 – October 2017 LP8860-Q1
PRODUCTION DATA.
Address 0x70
EEPROM Register 16 | |||||||
---|---|---|---|---|---|---|---|
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BOOST_EN_IRAMP_DELAY | BOOST_EXT_CLK_SEL | BOOST_IMAX_SEL[2:0] | BOOST_GD_VOLT |
Name | Bit | Access | Description |
---|---|---|---|
BOOST_EN_IRAMP_DELAY | 5 | R/W | Boost current ramp delay enable (for adjusting conversion ratio/stability, 35% of period)
1 = Delay enabled 0 = Delay disabled |
BOOST_EXT_CLK_SEL | 4 | R/W | Boost clock selection
0 = Internal clock 1 = External clock (SYNC pin) If external clock selected and sync disappears for 1.5…2 periods, boost automatically switches to using internal oscillator with frequency defined by BOOST_FREQ_SEL[2:0] |
BOOST_IMAX_SEL[2:0] | 3:1 | R/W | Maximum current limit for boost SW mode. Values below based on 25-mΩ sense resistor value.
000 = 2 A 001 = 3 A 010 = 4 A 011 = 5 A 100 = 6 A 101 = 7 A 110 = 8 A 111 = 9 A |
BOOST_GD_VOLT | 0 | R/W | Boost gate driver voltage selection
1 = Charge pump output (VGATE DRIVER> 6 V) 0 = VDD |